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HT37Q70/60/50/40/30/20 4-Channel Music Synthesizer MCU
Technical Document
* Tools Information www..com * FAQs * Application Note - HA0075E MCU Reset and Oscillator Circuits Application Note
Features
* Operating voltage: * 16-bit table read instructions for any bank/page read * Support 16 to 28 bidirectional I/O lines * Integrated 1-ch mono 16-bit DAC
3.6V~5.5V (HT37Q70/60) 3.3V~5.5V (HT37Q50/40) 2.4V~5.5V (HT37Q30/20)
* Operating frequency: typical 11.059MHz * Oscillation modes for the Oscillator clock
converter
* Integrated power Amplifier * Four channel polyphonic synthesizer * Low voltage reset (Tolerance 10%) * External interrupt INT * External 2 Timer clock input * 4 or 8 touch switch input * ADPCM decoder * Bit manipulation instructions * 63 powerful instructions * All instructions in 1 or 2 machine cycles
fOSC: Crystal (11.059MHz) 1-pin RC oscillation typ. 11.059MHz
* Built-in 8-bit MCU (HT-8) with 3208 bits RAM * Built-in 32K16-bits to 256K16-bits ROM for
program/data shared
* Eight-level subroutine nesting * Two 8 bit timer and one 16 bit timer * Watchdog timer * Power-down and Wake-up features for power saving
operation
General Description
The device is an 8-bit high performance RISC architecture microcontroller specifically designed for various Music and ADPCM applications. It provides an 8-bit MCU and 4-channel Wavetable synthesizer. It has a integrated 8-bit micro controller which controls the synthesizer to generate the melody by setting the special register. A Power-down function is included to reduce power consumption.
Selection Table
Most features are common to all devices, the main feature distinguishing them are Program Memory capacity, I/O count, DAC output, R2F input and package types. The following table summarizes the main features of each device.
Part No. VDD Channel OSC Program ROM 32K16bit 2.4V~ 5.5V HT37Q30 HT37Q40 HT37Q50 HT37Q60 HT37Q70 3.3V~ 5.5V 3.6V~ 5.5V 11.059 MHz 64K16bit 96K16bit 128K16bit 192K16bit 256K16bit 20 28 28 28 28 RAM I/O D/A Power AMP 3/4 O O O O O CR/F LVR 2.2V/ 3.3V 2.2V/ 3.3V 3.0V 8 8 3.3V 8 Package Types 20/28SOP 28SOP, 48SSOP
HT37Q20
16
4
8 8
2+2
3208bit
1ch-mono
28SOP, 64QFP, 80LQFP
Rev. 1.00
1
February 17, 2009
HT37Q70/60/50/40/30/20
Block Diagram
M id i E n g in e Code ADPCM Code W a tc h d o g T im e r O s c illa to r W a tc h d o g T im e r Low V o lta g e R eset
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R O M P ro g ra m M e m o ry
R A M D a ta M e m o ry
S ta c k
D /A C o n v e rts
8 - b it R IS C C o re I/O P o rts 1 6 /8 - b it T im e r s In te g ra te d P o w e r A m p lifie r R C /C ry s ta l O s c illa to r In te rru p t C o n tr o lle r
C R /F
Pin Assignment
NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OSC2 OSC1 RES PC0 1 2 3 4 5 6 7 8 9 10 PC1 PC2 PC3 OSC2 OSC1 RES VSS VDD VSS_DAC 20 19 18 17 16 15 14 13 12 11 H T37Q 20 2 0 S O P -A PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 RCH VD D_DAC VSS VDD VSS_DAC VD D_DAC NC RCH A U D _ IN V B IA S SP1 VSS_AM P 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NC NC PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC NC SP0 VD D_AM P PD2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 OSC2 OSC1 RES VSS VDD VSS_DAC VD D_DAC NC RCH A U D _ IN V B IA S SP1 VSS_AM P 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PD0 PD1 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC NC SP0 VD D_AM P PC0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PC1 PC2 PC3 PD0 PD1 PD2 PD3 OSC2 OSC1 RES VSS VDD VSS_DAC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC NC NC NC RCH VD D_DAC
H T 3 7 Q 7 0 /6 0 /5 0 /4 0 2 8 S O P -A
H T37Q 30 2 8 S O P -A
H T37Q 20 2 8 S O P -A
PD0 PD1 PD2 PD3 NC NC NC OSC2 OSC1 9 RES NC NC NC VSS VDD VSS_DAC VD D_DAC NC RCH A U D _ IN V B IA S SP1 VSS_AM P VD D_AM P 8 7 6 5 4 3 2 1
48 47 46 45 44 43 42 41 40 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 NC NC NC NC NC NC NC SP0 NC NC NC NC NC NC OSC2 7 8 9 10 11 12 13 14 15 16 17 18 19 OSC1 RES VSS VDD VSS_DAC VD D_DAC NC RCH A U D _ IN V B IA S SP1 VSS_AM P 6 5 4 3 2 1
NC VD D_AM P
64 63 62 61 60
20 21 22 23 24 SP0 PB0 PB1 PB2
NC
NC
NC
H T 3 7 Q 7 0 /6 0 /5 0 /4 0 6 4 Q F P -A
NC
NC PB3
59 58 57 56 55 54 53 52
25 26 27 28 29 30 31 32 PB4 PB5 PB6 PB7 VDD VSS
NC
NC
NC
NC
NC
NC
NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 R OS R V V VSS_D VD D_D OS NC NC NC NC NC NC NC NC NC NC C2 C1 ES SS DD AC AC NC CH NC
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 3435 36 3738 39 40 8 7 6 5 4 3 2 1 80 79 78 77 76 75 74 73 72 71 70 69 68 6766 65 6463 62 61
60 59 58 57 56 55 54 53 52 51 40 49 48 47 46 45 44 43 42 41
H T 3 7 Q 7 0 /6 0 /5 0 /4 0 8 0 L Q F P -A
PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
VSS VDD PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 NC NC NC NC SP0 VDD VSS SP1 V B IA AUD _AM P _AM P S _ IN
PA0
H T37Q 30 4 8 S S O P -A
Rev. 1.00
2
February 17, 2009
HT37Q70/60/50/40/30/20
Pin Assignment
HT37Q70/60
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(0 ,0 )
OSC2 OSC1 RES NC NC 2
1 3 4 5 6 7 8 9 10 11 12
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
NC VSS VDD VSS_DAC VD D_DAC NC RCH
13
14
15
16
17
18
19
20
21 22 PB1 PB0
23 24 PB2 PB3
25 PB4
26 27 PB5 PB6
28 PB7
29
30
31
Chip size: 23255155 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
A U D _ IN
V B IA S
SP1
VSS_AM P
VD D_AM P
VD D_AM P
VSS_AM P
SP0
VDD
VSS
Rev. 1.00
3
February 17, 2009
HT37Q70/60/50/40/30/20
HT37Q50/40
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OSC2 1 2 OSC1 RES
(0 ,0 )
50 49 48
PD3 PD2 PD1 PD0 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
3 4 5 6 7 8 9 10 11 12
47 NC NC NC VSS VDD VSS_DAC VD D_DAC NC RCH 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PB7 29 30 31
Chip size: 23254070 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
A U D _ IN
V B IA S
SP1
VSS_AM P
VD D_AM P
VD D_AM P
VSS_AM P
SP0
VDD
VSS
Rev. 1.00
4
February 17, 2009
HT37Q70/60/50/40/30/20
HT37Q30
PD3 40 PD2 39 PD1 38 PD0 37 PC7 36 PC6 35 PC5 34 PC4 33 32 31 30 29 28 27 26 25 24 23 22 21 OSC2 1 2 3 4 5 6 7 8 9 10 11 12 (0 ,0 ) OSC1 RES NC NC NC VSS VDD VSS_DAC VD D_DAC NC RCH PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
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13
14
15
16
17
18
19
20
Chip size: 23603325 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
A U D _ IN
V B IA S
SP1
VSS_AM P
VD D_AM P
VD D_AM P
VSS_AM P
SP0
Rev. 1.00
5
February 17, 2009
HT37Q70/60/50/40/30/20
HT37Q20
PD0 1 PC3 27 PC2 26 PC1 25 PC0 24 PA7 23 PA6 22 PA5 21 20 19 PD1 2 3 4 PD2 PD3 18 17 16 PA4 PA3 PA2 PA1 PA0
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(0 ,0 )
OSC2 OSC1 RES NC NC NC VSS 7 6
5
8 9 10 11 12 13 14 15 RCH
VSS_DAC
VD D_DAC
Chip size: 22302735 (mm)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
VDD
Rev. 1.00
6
February 17, 2009
HT37Q70/60/50/40/30/20
Pad Coordinates
HT37Q70/60 Pad No. X -1012.900 -1012.900 -1012.900 -1013.195 -1013.195 -1013.195 -998.595 -998.595 -971.945 -974.895 -975.025 -975.025 -1057.200 -954.200 -822.375 -715.426 -608.475 -480.425 -373.474 -266.525 -112.350 -9.350 85.650 188.650 283.650 Y -531.665 -630.665 -729.665 -899.560 -999.560 -1099.560 -1206.810 -1311.415 -1412.145 -1568.917 -1685.445 -1790.745 -2363.935 -2363.935 -2389.970 -2389.970 -2389.970 -2389.970 -2389.970 -2389.970 -2427.900 -2427.900 -2427.900 -2427.900 -2427.900 Pad No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X 386.650 481.650 584.650 745.620 847.745 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 Y -2427.900 -2427.900 -2427.900 -2383.710 -2391.950 -2393.440 -2290.440 -2195.440 -2092.440 -1997.440 -1894.440 -1799.440 -1696.441 -1601.440 -1498.440 -1403.440 -1300.440 -1205.440 -1102.440 -1007.440 -904.440 -809.440 -708.240 -605.240 -510.240 Unit: mm X -1012.900 -1012.900 -1012.900 -1013.195 -1013.195 -1013.195 -998.595 -998.595 -971.945 -974.895 -975.025 -975.025 -1057.200 -954.200 -822.375 -715.426 -608.475 -480.425 -373.474 -266.525 -112.350 -9.350 85.650 188.650 283.650 Y 9.835 -89.165 -188.165 -358.060 -458.060 -558.060 -665.310 -769.915 -870.645 -1027.417 -1143.945 -1249.245 -1822.435 -1822.435 -1848.470 -1848.470 -1848.470 -1848.470 -1848.470 -1848.470 -1886.400 -1886.400 -1886.400 -1886.400 -1886.400 Pad No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 X 386.650 481.650 584.650 745.620 847.745 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 1012.900 Y -1886.400 -1886.400 -1886.400 -1842.210 -1850.450 -1851.940 -1748.940 -1653.940 -1550.940 -1455.940 -1352.940 -1257.940 -1154.940 -1059.940 -956.940 -861.940 -758.940 -663.940 -560.940 -465.940 -362.940 -267.940 -166.740 -63.740 31.260 Unit: mm
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1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
HT37Q50/40 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Rev. 1.00
7
February 17, 2009
HT37Q70/60/50/40/30/20
HT37Q30 Pad No. 1 2 X -1031.100 -1031.100 -1031.100 -1038.550 -1038.550 -1038.550 -1016.795 -1016.795 -1028.020 -1030.970 -1031.100 -1031.100 -1075.000 -972.400 -840.575 -733.626 -626.675 -498.625 -391.674 -284.725 Y 306.920 207.920 102.485 -69.700 -156.700 -243.700 -336.210 -442.465 -537.520 -688.142 -804.670 -909.970 -1449.785 -1449.785 -1475.820 -1475.820 -1475.820 -1475.820 -1475.820 -1475.820 Pad No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 X 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 1031.340 777.240 674.240 579.240 476.240 381.240 280.190 177.190 82.190 Y 405.950 508.950 603.950 706.950 801.950 904.950 999.950 1102.950 1197.950 1300.950 1395.950 1498.950 1513.750 1513.750 1513.750 1513.750 1513.750 1513.750 1513.750 1513.750 Unit: mm X -957.220 -966.120 -966.120 -966.120 -966.120 -966.120 -966.120 -964.415 -964.415 -964.415 -962.015 -647.840 -534.220 -427.120 Y 1218.355 956.015 853.015 758.015 -580.625 -679.625 -785.055 -931.730 -1018.730 -1105.730 -1202.625 -1180.218 -1183.955 -1188.955 Pad No. 15 16 17 18 19 20 21 22 23 24 25 26 27 X -305.520 966.120 966.120 966.120 966.120 966.120 757.770 662.770 559.770 -561.220 -664.220 -759.220 -862.220 Y -1218.355 813.375 916.375 1011.375 1114.375 1209.375 1218.355 1218.355 1218.355 1218.355 1218.355 1218.355 1218.355 Unit: mm
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3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
HT37Q20 Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14
Rev. 1.00
8
February 17, 2009
HT37Q70/60/50/40/30/20
Pad Description
HT37Q70, HT37Q60, HT37Q50, HT37Q40 Pad Name I/O 3/4 3/4 3/4 3/4 3/4 3/4 Configuration Option 3/4 3/4 3/4 3/4 3/4 3/4 Positive digital power supply Positive DAC circuit power supply Positive power Amp. power supply Negative digital power supply, ground Negative DAC power supply, ground Negative AMP power supply, ground Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if all pins on this port have pull-high resistors. Pins PA5, PA6 and PA7 are pin-shared with INT, TMR0 and TMR1, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on this port have pull-high resistors. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on this port have pull-high resistors. Pins PC0 ~ PC7 are pin-shared with K0 and K7, respectively (K0~K7 are CR/F function). Bi-directional 4-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by pull-high option: by option). Pins PD0~PD3 are pin-shared with CR/F OSC input pins RCOUT, RR, RC and CC. RCOUT, RR, RC and CC control pin for CR/F Function. Audio right channel output Power Amp. output pins Power Amp. input pin Power Amp. voltage bias reference pin. Schmitt Trigger reset input, active low OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/8 frequency. No connection Function
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VDD_DAC VDD_AMP VSS VSS_DAC VSS_AMP PA0~PA4 PA5/INT PA6/TMR0 PA7/TMR1
I/O
Pull-high Wake-up
PB0~PB7
I/O
Pull-high
PC0/K0~ PC7/K7
I/O
Pull-high
PD0/RCOUT PD1/RR PD2/RC PD3/CC RCH SP1, SP0 AUD_IN VBIAS RES OSC1 OSC2 NC
I/O
Pull-high
O O I O I I O 3/4
3/4 3/4 3/4 3/4 3/4
Crystal or RC
3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors. 3. Because the two timers are used by MIDI the external timer pin functions are disabled.
Rev. 1.00
9
February 17, 2009
HT37Q70/60/50/40/30/20
HT37Q30 Pad Name VDD VDD_DAC www..com VDD_AMP VSS VSS_DAC VSS_AMP PA0~PA4 PA5/INT PA6/TMR0 PA7/TMR1 I/O 3/4 3/4 3/4 3/4 3/4 3/4 Configuration Option 3/4 3/4 3/4 3/4 3/4 3/4 Positive digital power supply Positive DAC circuit power supply Positive power Amp. power supply Negative digital power supply, ground Negative DAC power supply, ground Negative AMP power supply, ground Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if all pins on this port have pull-high resistors. Pins PA5, PA6 and PA7 are pin-shared with INT, TMR0 and TMR1, respectively. Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on this port have pull-high resistors. Pins PC0 ~ PC7 are pin-shared with K0 and K7, respectively (K0~K7 are CR/F function). Bi-directional 4-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by pull-high option: by option). Pins PD0~PD3 are pin-shared with CR/F OSC input pins RCOUT, RR, RC and CC. RCOUT, RR, RC and CC control pin for CR/F Function. Audio right channel output Power Amp. output pins Power Amp. input pin Power Amp. voltage bias reference pin. Schmitt Trigger reset input, active low OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/8 frequency. No connection Function
I/O
Pull-high Wake-up
PC0/K0~ PC7/K7
I/O
Pull-high
PD0/RCOUT PD1/RR PD2/RC PD3/CC RCH SP1, SP0 AUD_IN VBIAS RES OSC1, OSC2 NC
I/O
Pull-high
O O I O I I O 3/4
3/4 3/4 3/4 3/4 3/4
Crystal or RC
3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors. 3. Because the two timers are used by MIDI the external timer pin functions are disabled.
Rev. 1.00
10
February 17, 2009
HT37Q70/60/50/40/30/20
HT37Q20 Pad Name VDD VDD_DAC www..com VSS VSS_DAC PA0~PA4 PA5/INT PA6/TMR0 PA7/TMR1 I/O 3/4 3/4 3/4 3/4 Configuration Option 3/4 3/4 3/4 3/4 Positive digital power supply Positive DAC circuit power supply Negative digital power supply, ground Negative DAC power supply, ground Bidirectional 8-bit input/output port. Each pin can be configured as a wake-up input by configuration option. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine if all pins on this port have pull-high resistors. Pins PA5, PA6 and PA7 are pin-shared with INT, TMR0 and TMR1, respectively. Bidirectional 4-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. A configuration option determines if all pins on this port have pull-high resistors. Pins PC0 ~ PC3 are pin-shared with K0 and K3, respectively (K0~K3 are CR/F function). Bi-directional 4-bit I/O port. Software instructions determined the CMOS output or Schmitt trigger with a pull-high resistor (determined by pull-high option: by option). Pins PD0~PD3 are pin-shared with CR/F OSC input pins RCOUT, RR, RC and CC. RCOUT, RR, RC and CC control pin for CR/F Function. Audio right channel output Schmitt Trigger reset input, active low OSC1, OSC2 are connected to an external RC network or external crystal, determined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/8 frequency. No connection Function
I/O
Pull-high Wake-up
PC0/K0~ PC3/K3
I/O
Pull-high
PD0/RCOUT PD1/RR PD2/RC PD3/CC RCH RES OSC1 OSC2 NC
I/O
Pull-high
O I I O 3/4
3/4 3/4
Crystal or RC
3/4
Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have pull-high resistors. 3. Because the two timers are used by MIDI the external timer pin functions are disabled.
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+5.5V Input Voltage .............................VSS-0.3V to VDD+0.3V IOL Total ..............................................................150mA Total Power Dissipation .....................................500mW Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. Storage Temperature ...........................-50C to 125C Operating Temperature ..........................-20C to 70C IOH Total............................................................-100mA
Rev. 1.00
11
February 17, 2009
HT37Q70/60/50/40/30/20
D.C. Characteristics
Test Conditions Symbol Parameter VDD Conditions fOSC=11.059MHz for HT37Q30/20 Operating Voltage 3/4 fOSC=11.059MHz for HT37Q50/40 fOSC=11.059MHz for HT37Q70/60 IDD Operating Current (Crystal OSC or RC OSC) 3V No load, fOSC=8MHz~12.8MHz, 5V DAC disable 3V No load, system HALT, 5V WDT disable 3V No load, system HALT, 5V WDT enable 3/4 3/4 3/4 3/4 3V VOL=0.1VDD 5V IOH I/O Port Segment Logic Output Source Current Pull-high Resistance of I/O Ports 5V 3V 5V 3V 3/4 3/4 LVR 2.2V option VLVR Low Voltage Reset Voltage 5V LVR 3.0V option LVR 3.3V option IO IADC AUD Current Source Additional Power Consumption if A/D Converter is Used 3/4 3V 5V VOH=0.9VDD 3/4 (THD+N)/S1%, RL=8W VIN=1kHz Sinewave (THD+N)/S10%, RL=8W VIN=1kHz Sinewave PO Internal AMP Output Power 5V (THD+N)/S1%, RL=8W VIN=1kHz Sinewave (THD+N)/S10%, RL=8W VIN=1kHz Sinewave Note: LVR 3.0V only applies to HT37Q50 and HT37Q40. VOH=0.9VDD 10 -2 -5 20 10 2.0 2.7 3.0 3/4 3/4 3/4 3/4 3/4 3/4 3/4 25 -4 -8 60 30 2.2 3.0 3.3 -3 0.5 1.5 90 125 385 490 3/4 3/4 3/4 100 50 2.4 3.3 3.6 3/4 1 3 3/4 3/4 3/4 3/4 mA mA mA kW kW V V V mA mA mA mW mW mW mW 3/4 3/4 3/4 3/4 2.4 3.3 3.6 3/4 3/4 3/4 3/4 3/4 3/4 0 0.7VDD 0 0.9VDD 6 3.0 4.5 4.5 2 8 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 12 5.5 5.5 5.5 8 16 1 2 5 10 0.3VDD VDD 0.4VDD VDD 3/4 V V V mA mA mA mA mA mA V V V V mA Min. Typ. Max. Unit Ta=25C
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VDD
ISTB1
Standby Current (WDT Disable)
ISTB2 VIL1 VIH1 VIL2 VIH2
Standby Current (WDT Enable) Input Low Voltage for I/O Ports Input High Voltage for I/O Ports Input Low Voltage (RES) Input High Voltage (RES) I/O Port Segment Logic Output Sink Current
IOL
RPH
3V
Rev. 1.00
12
February 17, 2009
HT37Q70/60/50/40/30/20
A.C. Characteristics
Test Conditions Symbol Parameter VDD Conditions 2.4V~5.5V Oscillator Clock (Crystal OSC/RC OSC) 3/4 3.3V~5.5V 3.6V~5.5V tWDTOSC Watchdog Oscillator Period tRES tSST tLVR External Reset Low Pulse Width System Start-up Timer Period Low Voltage Width to Reset 3V 5V 3/4 3/4 3/4 3/4 3/4 3/4 Power-up or wake-up from HALT 3/4 8000 8000 8000 45 32 1 3/4 0.25 11059 11059 11059 90 65 3/4 1024 1.00 12800 12800 12800 180 130 3/4 3/4 2.00 kHz ms ms ms tSYS ms kHz Min. Typ. Max. Unit Ta=25C
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Note: tSYS= 1/fSYS fSYS=fOSC/2
Characteristics Curves
R v s . F C h a rt
16 14 F re q u e n c y (M H z ) 12 10 8 6 4 82 91 100 R 115 (k W ) 120 150 180 4 .5 V 3 .0 V
V v s . F C h a r t (F o r 3 .0 V &
16 15 F re q u e n c y (M H z ) 14 13 12 11 10 9 8 2 .4 2 .6 2 .8 3 .0 3 .2 3 .4 3 .6 V 3 .8
DD
4 .5 V )
1 1 .0 5 9 M H z /1 0 0 k W
(4 .5 V )
1 1 .0 5 9 M H z /1 1 5 k W
(3 V )
4 .0 (V )
4 .2
4 .4
4 .6
4 .8
5 .0
5 .2
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(THD+N) vs. Output Power
RLOAD=8W, VIN=1kHz Sinewave for 3.0V
%
100
www..com 50
20 10 5 2 1 0 .5 0 .2 0 .1 0 .0 5 0 .0 2 0 .0 1 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 2 5
O u tp u t P o w e r (W )
RLOAD=8W, VIN=1kHz Sinewave for 5.0V
%
100 50 20 10 5 2 1 0 .5 0 .2 0 .1 0 .0 5 0 .0 2 0 .0 1 1m 2m 5m 10m 20m 50m 100m 200m 500m 1 2 5
O u tp u t P o w e r (W )
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System Architecture
A key factor in the high-performance features of the Holtek range of Music Type microcontrollers is attributed to the internal system architecture. The range of devices take advantage of the usual features found www..com within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction execution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arithmetic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural features ensure that a minimum of external components is required to provide a functional I/O and A/D control system with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crystal/Resonator or RC oscillator. The oscillator frequency divided by 2 is subdivided into four internally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one
T1 T2 T3 T4 T1
instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of fOSC/8 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as JMP or CALL, that demand a jump to a non-consecutive Program Memory address. Note that the Program Counter width varies with the Program Memory capacity depending upon which device is selected. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by user.
T2 T3 T4 T1 T2 T3 T4
S y s te m
C lo c k o f M C U (fS Y S = fO S C /2 ) C o u n te r
P ro g ra m
PC
PC+1
PC+2
P ip e lin in g
F e tc h In s t. (P C ) E x e c u te In s t. (P C -1 )
F e tc h In s t. (P C + 1 ) E x e c u te In s t. (P C )
F e tc h In s t. (P C + 2 ) E x e c u te In s t. (P C + 1 )
System Clocking and Pipelining
1 2 3 4 5 6 D ELAY: : :
M O V A ,[1 2 H ] C ALL D ELAY C P L [1 2 H ]
F e tc h In s t. 1
E x e c u te In s t. 1 F e tc h In s t. 2 E x e c u te In s t. 2 F e tc h In s t. 3 F lu s h P ip e lin e F e tc h In s t. 6 E x e c u te In s t. 6 F e tc h In s t. 7
NOP
Instruction Fetching
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When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For conditional www..com skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is discarded and a dummy cycle takes its place while the correct instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and is a readable and writable register. By transferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessible under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack can have 8 levels depending upon which option is selected and is neither part of the data nor part of the program space, and is neither readable nor writable. The activated level is indexed by the Stack Pointer, SP, and is neither readable nor writable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. Program Counter Mode b17~b13 Initial Reset Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Timer Counter 2 Overflow ERCOCI Interrupt ADPCM Interrupt Skip Loading PCL Jump, Call Branch Return from Subroutine P17~P13 00000 00000 00000 00000 00000 00000 b12 b11 b10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 b9 0 0 0 0 0 0 b8 0 0 0 0 0 0 b7 0 0 0 0 0 0 b6 0 0 0 0 0 0 b5 0 0 0 0 0 0 b4 0 0 0 1 1 1 b3 0 1 1 0 0 1 b2 0 0 1 0 1 0 b1 0 0 0 0 0 0 b0 0 0 0 0 0 0
Program Counter + 2 (Within Current Bank) P12 P11 P10 P9 #9 S9 P8 #8 S8 @7 #7 S7 @6 #6 S6 @5 #5 S5 @4 #4 S4 @3 #3 S3 @2 #2 S2 @1 #1 S1 @0 #0 S0
BP1.4~BP1.0 #12 #11 #10 S17~S13 S12 S11 S10
Program Counter Note: P17~P8: Program Counter bits @7~@0: PCL bits #12~#0: Instruction code address bits BP1.4~BP1.0: ROM bank pointer S17~S0: Stack register bits For the HT37Q70/60, the Program Counter is 18 bits wide, i.e. from b17~b0. For the HT37Q50/40, the Program Counter is 17 bits wide, i.e. from b16~b0, therefore the b17 column in the table is not applicable. For the HT37Q30, the Program Counter is 16 bits wide, i.e. from b15~b0, therefore the b17 and b16 the columns in the table are not applicable. For the HT37Q20, the Program Counter is 15 bits wide, i.e. from b14~b0, therefore the b17, b16 and b15 the columns in the table are not applicable.
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P ro g ra m C o u n te r
T o p o f S ta c k S ta c k www..comt e r P o in
S ta c k L e v e l 1 S ta c k L e v e l 2 S ta c k L e v e l 3 P ro g ra m M e m o ry
16 bits depending upon which device is selected. The Program Memory is addressed by the Program Counter and ROM bank point, and also contains general data, Wave table data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are reserved for special usage such as reset and interrupts.
* Location 000H
B o tto m
o f S ta c k
S ta c k L e v e l 8
If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine instruction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Arithmetic and Logic Unit - ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic operations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related instruction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or operations may result in carry, borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:
* Arithmetic operations: ADD, ADDM, ADC, ADCM,
This vector is reserved for use by the device reset for program initialization. After a device reset is initiated, the program will jump to this location and begin execution.
* Location 004H
This vector is used by the external interrupt. If the external interrupt pin on the device goes low, the program will jump to this location and begin execution if the external interrupt is enabled and the stack is not full.
* Location 008H
This vector is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
* Location 00CH
This vector is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results from a Timer/Event Counter 1 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 00CH.
* Location 010H
SUB, SUBM, SBC, SBCM, DAA
* Logic operations: AND, OR, XOR, ANDM, ORM,
XORM, CPL, CPLA
* Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA,
RLC
* Increment and Decrement INCA, INC, DECA, DEC * Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ,
This vector is reserved for the Timer Counter 2 interrupt service program. If a timer interrupt results from a Timer Counter 2 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 0010H.
* Location 014H
SIZA, SDZA, CALL, RET, RETI
Program Memory
The Program Memory is the location where the user code or program is stored. The type of memory is the mask ROM memory. It offer the most cost effective solutions for high volume products. Structure The Program Memory has a capacity of 256K by 16, 192K by 16, 128K by 16, 96K by 16, 64K by 16 or 32K by
This vector is reserved for the ERCOCI interrupt service program. If an external RC oscillation converter interrupt results from an external RC oscillation converter interrupt is activated, and the stack is not full, the program begins execution at location 0014H.
* Location 018H
This vector is reserved for the Adpcm interrupt service program. If a Adpcm interrupt results, and if the interrupt is enabled and the stack is not full, the program begins execution at location 0018H.
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000H 004H H T37Q 70 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r T im e r /E v e n t C o u n te r 2 In te rru p t V e c to r ERCOCI In te rru p t V e c to r ADPCM In te rru p t V e c to r 000H 004H 008H 00CH 010H 014H H T37Q 60 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r T im e r /E v e n t C o u n te r 2 In te rru p t V e c to r ERCOCI In te rru p t V e c to r ADPCM In te rru p t V e c to r 000H 004H 008H 00CH 010H 014H H T37Q 50 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r T im e r /E v e n t C o u n te r 2 In te rru p t V e c to r ERCOCI In te rru p t V e c to r ADPCM In te rru p t V e c to r
www..com 0 0 8 H
00CH 010H 014H
018H 01C H 1FFFH
018H 01C H 1FFFH
018H 01C H 1FFFH
B ank1~31 (B P 1 [4 :0 ]= [1 ]~ [1 F H ]) 2FFFFH 3FFFFH 1 6 b its
B ank1~23 (B P 1 [4 :0 ]= [1 ]~ [1 7 H ]) 1FFFFH 1 6 b its
B ank1~15 (B P 1 [3 :0 ]= [1 ]~ [0 F H ]) 1 6 b its
000H 004H 008H 00CH 010H 014H
H T37Q 40 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r T im e r /E v e n t C o u n te r 2 In te rru p t V e c to r ERCOCI In te rru p t V e c to r ADPCM In te rru p t V e c to r
000H 004H 008H 00CH 010H 014H
H T37Q 30 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r T im e r /E v e n t C o u n te r 2 In te rru p t V e c to r ERCOCI In te rru p t V e c to r ADPCM In te rru p t V e c to r
000H 004H 008H 00CH 010H 014H
H T37Q 20 In itia lis a tio n V e c to r E x te rn a l In te rru p t V e c to r T im e r /E v e n t C o u n te r 0 In te rru p t V e c to r T im e r /E v e n t C o u n te r 1 In te rru p t V e c to r T im e r /E v e n t C o u n te r 2 In te rru p t V e c to r ERCOCI In te rru p t V e c to r ADPCM In te rru p t V e c to r
018H 01C H 1FFFH
018H 01C H 1FFFH
018H 01C H 1FFFH
17FFFH
B ank1~11 (B P 1 [3 :0 ]= [1 ]~ [0 B H ]) 1 6 b its
FFFFH
B ank1~7 (B P 1 [2 :0 ]= [1 ]~ [7 ]) 1 6 b its
7FFFH
B ank1~3 (B P 1 [1 :0 ]= [1 ]~ [3 ]) 1 6 b its
Program Memory Structure
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Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the address of the look up data www..com retrieved in the three table pointer registers, TBLP, to be TBMP and TBHP. This three registers define the address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory or last Program Memory page in the specific bank which defined by bank point register as BP1 using the TABRDC[m] or TABRDL [m] instructions, respectively. When these instructions are executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will have uncertain values. The following diagram illustrates the addressing/data flow of the look-up table:
TBHP1 TBM P1 TBLP1 P ro g ra m M e m o ry
Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the HT37Q70/60/50/30/40/20 microcontroller. This example uses raw table data located in the last page which is stored there using the ORG and ROMbank statement. The value at this ORG statement is 3F00H which refers to the start address of the last page within the Program Memory of the HT37Q70/60/50/40/30/20 microcontroller. The table pointer is setup here to have an initial value of 06H. This will ensure that the first data read from the data table will be at the Program Memory address 3F06H or 6 locations after the start of the last page in selected ROMbank. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the TABRDL [m] instruction is executed. Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.
TBLH H ig h B y te o f T a b le C o n te n ts
S p e c ifie d b y [m ] Low B y te o f T a b le C o n te n ts
Instruction
Table Location Bits b17~b13 BP1_4~BP1_0 b12~b8 11111 b7 @7 b6 @6 @6 b5 @5 @5 b4 @4 @4 b3 @3 @3 b2 @2 @2 b1 @1 @1 b0 @0 @0
TABRDC [m] TBHP1_1~TBMP1_5 TBMP1_4~TBMP1_0 @7 TABRDL [m]
Table Location Note: @7~@0: Table pointer lower-order bits are TBLP1 [7:0] b17~b0: Current program ROM table address A [17:0] TBMP1_4~TBMP1_0: TBMP1 bit 4 ~0 TBHP1_1~TBMP1_5: TBHP1 (bit 1 ~0) to TBMP1 (bit7 ~5) BP1_4 ~BP1_0: Bits of bank BP1 bit0~4 For the HT37Q70/60, the Table address location is 18 bits wide, i.e. from b17~b0. For the HT37Q50/40, the Table address location is 17 bits wide, i.e. from b16~b0. For the HT37Q30, the Table address location is 16 bits wide, i.e. from b15~b0. For the HT37Q20, the Table address location is 15 bits wide, i.e. from b14~b0.
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tempreg1 tempreg2 tempreg3 tempreg4 db db db db ? ? ? ? ; ; ; ; temporary temporary temporary temporary register register register register #1 #2 #3 #4
: : mov a,01h www..com bp1,a mov mov a,06h mov tblp1,a clr tbmpl clr tbhpl : : tabrdl tempreg1
; set ROM bank 1 point ; initialise table pointer ; to the last page
; ; ; ;
transfers value in table referenced by table pointer to tempregl data at prog. memory address 3F06H transferred to tempreg1 and TBLH
dec tblp1 tabrdl tempreg2
; reduce value of table pointer by one ; ; ; ; ; ; ; ; transfers value in table referenced by table pointer to tempreg2 data at prog.memory address 3F05H transferred to tempreg2 and TBLH in this example the data 1AH is transferred to tempreg1 and data 0FH to register tempreg2 the value 00H will be transferred to the high byte register TBLH
: : mov a,04h mov tblp1,a mov a,3Fh mov tbmp1,a mov a,00h mov tbhp1,a tabrdc tempreg3 : : rombank 1 romsumvalue1; sets rombank 1 initial address of last page ;(for HT37Q70/60/50/40/30/20) romsumvalue1 .section at 1F00h code dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh : : ; initialise table pointer low byte ; ; initialise table pointer middle byte ; initialise table pointer high byte ;
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ROM Bank Pointer (2DH) The program memory is organized into 32/24/16/12/8/4 banks for HT37Q70/60/50/40/30/20 and each bank into 819216 bits of program ROM. BP1.7~BP1.0 is used as the bank pointer. After an instruction has been executed to write data to the BP1 register to select a different bank, note that the new bank will not be selected immediately. It is until the instruction JMP or CALL or interrupt has completed execution that the bank will be actually selected. www..com Register Bit No. Function 00000000b= Select ROM Bank0 (0000h~1FFFh) 00000001b= Select ROM Bank1 (2000h~3FFFh) 00000010b= Select ROM Bank2 (4000h~5FFFh) 00000011b= Select ROM Bank3 (6000h~7FFFh) : 00011110b= Select ROM Bank30 (3C000h~3DFFFh) 00011111b= Select ROM Bank31 (3E000h~3FFFFh)
BP1 (2DH)
0~7
Note: For the HT37Q70/60, the ROM bank point register is 5 bits wide effectively, i.e. from b4~b0. For the HT37Q50/40, the ROM bank point register is 4 bits wide effectively, i.e. from b3~b0. For the HT37Q30, the ROM bank point register is 3 bits wide effectively, i.e. from b2~b0. For the HT37Q20, the ROM bank point register is 2 bits wide effectively, i.e. from b1~b0.
RAM Data Memory
The RAM Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary information is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain protected from user manipulation. The second area of RAM Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control.
00H 5FH 60H S p e c ia l P u r p o s e D a ta M e m o ry
common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. Bank 1 of the RAM Data Memory is located at address 60H. The RAM data memory is designed with 3208 bits with 2 RAM banks. There are two RAM BANK pointers (RBP1 and RBP2 ) control Bank 0~1 (RBP1.0/RBP2.0) The data memory is designed with 256 bytes and divided into five functional groups: special function registers (00H~1FH), music synthesis controller registers (20H~2FH), ADPCM decoder controller register (30H~35H), the other function (35H~5FH) and general purpose data memory (60H~FFH). They are also indirectly accessible through Memory pointer registers MP0, MP1and MP2, where MP1/MP2 can deal with all banks of data memory but MP0 deal with Bank0 data memory only.
G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s ) 0FFH Bank 0
G e n e ra l P u rp o s e D a ta M e m o ry (1 6 0 B y te s )
RBP1 (04H) bit0 control MP1 RBP2 (2FH) bit0 control MP2 General Purpose Data Memory
Bank 1
Bank 0~Bank 1 RAM Data Memory Structure Structure The RAM Data Memory is subdivided into 2 banks, known as Bank 0 and Bank 1, all of which are implemented in 8-bit wide RAM. Most of the RAM Data Memory is located in Bank 0 which is also subdivided into two sections, the Special Purpose Data Memory and the General Purpose Data Memory. The start address of the Data Memory is the address 00H. Registers which are
All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user program for both read and write operations. The bank 0 data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. By using the SET [m].i and CLR [m].i instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory.
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Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, www..com the details of which are located under the relevant Special Function Register section. Note that for locations
H T 3 7 Q 7 0 /6 0 H T 3 7 Q 5 0 /4 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH DAH DAL DACC CHAN F re q N H F re q N L A d d rH A d d rL RepH RepL ENV A d d rH 1 LVC RVC TBM P1 TBHP1 BP1 FFH : U n u s e d , re a d a s "0 0 " 5FH 60H
G e n e ra l P u rp o s e D a ta M e m o ry (3 2 0 B y te s : 1 6 0 B y te s x 2 B a n k s )
that are unused, any read instruction to these addresses will return the value 00H. Although the Special Purpose Data Memory registers are located in Bank 0, they will still be accessible even if the Bank Pointer has selected Bank 1.
IA R 0 MP0 IA R 1 MP1 RBP1 ACC PCL TBLP1 TBLH W DTS STATUS IN T C TM R0H TM R0L TM R0C TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC
2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H
H T 3 7 Q 7 0 /6 0 H T 3 7 Q 5 0 /4 0 MP2 RBP2 ADR XSPL XSPH ADPC ADPS IN T C H TM R2L TM R2C TM R3L TM R3C
H T37Q 30 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC IA R 0 MP0 IA R 1 MP1 RBP1 ACC PCL TBLP1 TBLH W DTS STATUS IN T C TM R0H TM R0L TM R0C
2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH
H T37Q 30 MP2 RBP2 ADR XSPL XSPH ADPC ADPS IN T C H TM R2L TM R2C TM R3L TM R3C
H T37Q 20 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H TM R1L TM R1C PA PAC PB PBC PC PCC PD PDC PE PEC DAH DAL DACC CHAN F re q N H F re q N L A d d rH A d d rL RepH RepL ENV A d d rH 1 LVC RVC TBM P1 BP1 IA R 0 MP0 IA R 1 MP1 RBP1 ACC PCL TBLP1 TBLH W DTS STATUS IN T C TM R0H TM R0L TM R0C
2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 5FH 60H
H T37Q 20 MP2 RBP2 ADR XSPL XSPH ADPC ADPS IN T C H TM R2L TM R2C
ASCR TM RAH TM RAL RCOCCR TM RBH TM RBL RCOCR
12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH
ASCR TM RAH TM RAL RCOCCR TM RBH TM RBL RCOCR
12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H
ASCR TM RAH TM RAL RCOCCR TM RBH TM RBL RCOCR ADRL ADRH ADCR ACSR SBCR SBDR R S232C TXD RXD PF PFC PG PGC BRGR
DAH DAL DACC CHAN F re q N H F re q N L A d d rH A d d rL RepH RepL ENV A d d rH 1 LVC RVC TBM P1 BP1
4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 5FH 60H
G e n e ra l P u rp o s e D a ta M e m o ry (3 2 0 B y te s :
2AH 2BH 2CH 2DH
G e n e ra l P u rp o s e D a ta M e m o ry (3 2 0 B y te s :
FFH
1 6 0 B y te s x 2 B a n k s )
FFH
1 6 0 B y te s x 2 B a n k s )
Data Memory Structure
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Special Function Registers
To ensure successful operation of the microcontroller, certain internal registers are implemented in the RAM Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, www..com watchdog, etc., as well as external functions such as I/O data control. The location of these registers within the RAM Data Memory begins at the address 00H. Indirect Addressing Register - IAR0, IAR1 The Indirect Addressing Registers, IAR0 and IAR1, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0 and IAR1 registers will result in no actual read or write operation to these registers but rather to the memory location specified by their corresponding Memory Pointer, MP0 or MP1/MP2. Acting as a pair, IAR0 and MP0 can together only access data from Bank 0, while the IAR1 and MP1/MP2 register can Example The following example shows how to clear General Purpose Data Memory of bank0 by using MP0 and bank0~bank1 by using MP1 and MP2 code .section at 0 code org 00h RAM0TEST: MOV A,60H MOV MP0,A ; loaded with first RAM address LOOP0: CLR IAR0 ; clear the data at address defined by MP0 CLR WDT SIZ MP0 ; increase MP0, and skip out if MP0 is 0 JMP LOOP0 : RAM1TEST: CLR DACC.7 ; access data to iar1 by MP1 CLR rBP1 ; clear RAM bank pointer 1 RAM1_MP1: MOV A,rBP1 ; load rBP1 data, and check if rBP1 is 25 XOR A,25 SZ ZERO ; jump to exit loop if rBP1 is 2 JMP RAM1TEST_Exit MOV A,60H ; loaded with first RAM address to MP1 MOV MP1,A LOOP1: CLR WDT CLR IAR1 ; clear the data at address defined by MP1 SIZ MP1 ; increase MP1, and skip out if MP1 is 0 JMP LOOP1 INC rBP1 ; increase rBP1 JMP RAM1_MP1 RAM1TEST_Exit: : RAM2TEST: Set dacc.7 ; access data to iar1 by MP2 CLR rBP2 ; clear RAM bank pointer 2 access data from both Bank 0 and Bank 1. Using MP1 or MP2 are selected by DACC.7. As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of 00H and writing to the registers indirectly will result in no operation. Memory Pointer - MP0, MP1, MP2 Three Memory Pointers, known as MP0, MP1 and MP2 are provided. These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data. When any operation to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to, is the address specified by the related Memory Pointer. MP0, together with Indirect Addressing Register, IAR0, are used to access data from Bank 0 only, while MP1/MP2 and IAR1 are used to access data from both Bank 0 and Bank 1. Using MP1 or MP2 are selected by DACC.7.
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RAM1MP2: MOV A,RBP2 XOR A,25 SZ ZERO JMP RAM2TEST_Exit MOV A,60H www..com MOV MP2,A LOOP2: CLR WDT CLR IAR1 SIZ MP2 JMP LOOP2 INC rBP2 JMP RAM1MP2 RAM2TEST_Exit: : Bank Pointer - RBP1, RBP2 The RAM Data Memory is divided into 2 Banks, known as Bank 0 to Bank 1. Selecting the required Data Memory area is achieved using the RAM Bank Pointers which are RBP1 and RBP2. The RBP1 and RBP2 match up with MP1 and MP2 respectively. If data in Bank 0 is to be accessed, then the RBP registers must be loaded with the value 00, while if data in Bank 1 is to be accessed, then the RBP registers must be loaded with the value 01. Using Memory Pointer MP0 and Indirect Addressing Register IAR0 will always access data from Bank 0, irrespective of the value of the Bank Pointer. The RBP1 and RBP2 register is located at memory location 60H in Bank 0 to Bank 1 and can only be accessed indirectly using two memory pointers MP1 and MP2 and the indirect addressing register IAR1 will always access data from Bank 0 to Bank 1. The Data Memory is initialized to Bank 0 to Bank 1 after a reset, except for the WDT time-out reset in the Power Down Mode, in which case, the Data Memory bank remains unaffected. It should be noted that Special Function Data Memory is not affected by the bank selection, which means that the Special Function Registers can be accessed from within Bank 0 to Bank 1. Directly addressing the Data Memory will always result in Bank 0 being accessed irrespective of the value of the Bank Pointer. Register Bit No. 0 1~7 Function RAM Bank Point 1 Select 0= Select RAM Bank0 1= Select RAM Bank1 Unused bit RBP1 (04H) Register Bit No. 0 1~7 Function RAM Bank Point 2 Select 0= Select RAM Bank0 1= Select RAM Bank1 Unused bit Look-up Table Registers - TBLP1, TBMP1, TBHP1, TBLH These seven special function registers are used to control operation of the look-up table which is stored in the Program Memory. TBLP1, TBMP1 and TBHP1 are the table pointer and indicate the location where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the INC or DEC instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. 24 February 17, 2009
; jump to exit loop if rBP2 is 2 ; loaded with first RAM address to MP2
; clear the data at address defined by MP2 ; increase MP2, and skip out if MP2 is 0 ; increase rBP2
Accumulator - ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register - PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.
RBP1
RBP2
RBP2 (2FH) Note: Using MP1 or MP2 are selected by DACC.7.
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Watchdog Timer Register - WDTS The Watchdog feature of the microcontroller provides an automatic reset function giving the microcontroller a means of protection against spurious jumps to incorrect Program Memory addresses. To implement this, a timer is provided within the microcontroller which will issue a www..com reset command when its value overflows. To provide variable Watchdog Timer reset times, the Watchdog Timer clock source can be divided by various division ratios, the value of which is set using the WDTS register. By writing directly to this register, the appropriate division ratio for the Watchdog Timer clock source can be setup. Note that only the lower 3 bits are used to set division ratios between 1 and 128. Status Register - STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system management flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, operations related to the status register may give different results due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the CLR WDT or HALT instruction. The PDF flag is affected only by executing the HALT or CLR WDT instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations.
* C is set if an operation results in a carry during an ad* AC is set if an operation results in a carry out of the
low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
* Z is set if the result of an arithmetic or logical operation
is zero; otherwise Z is cleared.
* OV is set if an operation results in a carry into the high-
est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
* PDF is cleared by a system power-up or executing the
CLR WDT instruction. PDF is set by executing the HALT instruction.
* TO is cleared by a system power-up or executing the
CLR WDT or HALT instruction. TO is set by a WDT time-out. In addition, on entering an interrupt sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Registers - INTC, INTCH The two 8-bit registers, known as the INTC and INTCH register which control the operation of both external and internal timer, CR/F and ADPCM interrupts, and By setting various bits within this register using standard bit manipulation instructions, the enable/disable function of the external and timer, CR/F and ADPCM interrupts can be independently controlled. A master interrupt bit within this register, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further interrupt and is set by executing the RETI instruction. Note: In situations where other interrupts may require servicing within present interrupt service routines, the EMI bit can be manually set by the program after the present interrupt service routine has been entered.
b0 TO PDF OV Z AC C
dition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
b7
S T A T U S R e g is te r
ith m e r r y fla x ilia r y r o fla g O v e r flo w g Ar Ca Au Ze tic /L o g ic O p e r a tio n F la g s c a r r y fla g fla g an n tim e a g e m e n t F la g s fla g e - o u t fla g n te d , re a d a s "0 "
S y s te m M Pow erdow W a tc h d o g N o t im p le m
Status Register
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Timer/Event Counter Registers - TMR0H, TMR0L, TMR1L, TMR2L, TMR0C, TMR1C, TMR2C HT37Q70/60/50/40/30/20 contains two 8-bit and a 16-bit Timer/Event Counters which has an associated register known as TMR0H and TMR0L. are the location where www..com the timers 16-bit value is located.TMR1L and TMR2L are the location where the timers 8-bit value is located. An associated control register, known as TMR0C, TMR1C and TMR2C contains the setup information for the timer. Input/Output Ports and Control Registers - PA, PB, PC, PD, PAC, PBC, PCC, PDC Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. with each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the control register must be set high, for an output it must be set low. During program initialization, it is important to first setup the control registers to specify which pins are outputs and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits using the SET [m].i and CLR [m].i instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control registers during normal program operation is a useful feature of these devices. D/A Converter Registers - DAH, DAL, DACC HT37Q70/60/50/40/30/20 provide one 16-bit D/A converters. The correct operation of the D/A requires the use of two data registers, and a control register. It contain a 16-bit D/A converter, there are two data registers, a high byte data register known as DAH, and a low byte data register known as DAL. These are the register locations where the digital value is placed before the completion of a digital to analog conversion cycle. The configuration of the D/A converter is setup via the control register DACC. Wavetable Function Registers CHANNEL_NUMBER, FREQ_NUMBER_H, FREQ_NUMBER_L, REPEAT_NUMBER_H, REPEAT_NUMBER_L, VOLUME_CONTROL, L_VOL, R_VOL HT37Q70/60/50/40/30/20 contains Wavetable synthesizer Function. The HT37Q70/60/50/40/30/20 has a built-in 8 output channels. CHANNEL_NUMBER is channel number selection. FREQ_NUMBER_H and FREQ_NUMBER_L are used to define the output speed of the PCM file. START_ADDRESS_H and START_ADDRESS_L is setup for the start address of the PCM code before Wavetable function implement. The repeat number register as known REPEAT_NUMBER_H and REPEAT_NUMBER_L are used to define the address which is the repeat point of the sample. When the repeat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80H) until the volume become close. It provides the left and right volume control independently. The 10-bit left and right volume are controlled by VOLUME_CONTROL, L_VOL, and R_VOL respectively. The VOLUME_CONTROL contain both left and right volume some bit of high byte. ADPCM Function Registers - ADR, XSPL, XSPH, ADPC, ADPS HT37Q70/60/50/40/30/20 contains ADPCM Decoder Function. The must set initial value of register known as XSPL and XSPH before implementing ADPCM Decoder procedure. There are two 4-bit ADPCM encode data of ADR. The data of ADR implement via ADPCM Decoder, and output 8-bit PCM data which is synthesized by MIDI synthesizer. The ADPC is the control register for the ADPCM Decoder. The ADPS is the status register for the ADPCM Decoder. CR/F Converter Registers - ASCR, TMRAH, TMRAL, RCOCCR, TMRBH, TMRBL, RCOCR There are 8 analog switch lines in the microcontroller for K0~K7 for HT37Q70/60/50/40/30, except HT37Q20 which only have 4 analog switch lines for K0~K3 and a corresponding Analog Switch control registers known as ASCR. The RC oscillation converter contains two 16-bit programmable count-up counters and the Timer A clock source may come from the system clock (fSYS=fOSC/2) or system clock/4 (fOSC/8). There are two data registers, a high byte data register known as TMRAH, and a low byte data register known as TMRAL. The timer B clock source may come from the external RC oscillator. There are two data registers, a high byte data register known as TMRBH, and a low byte data register known as TMRBL. There are two control and status registers known as RCOCCR and RCOCR.
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Input/Output Ports
Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of every pin fully under user program control, pull-high options for all ports and wake-up options on certain pins, www..com the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. Depending upon which device or package is chosen, the microcontroller range provides from 16 to 28 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These I/O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction MOV A,[m], where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor. To eliminate the need for these external resistors, I/O pins PA~PD, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via PA~PD option respectively, located in the configuration. The pull-high resistors are implemented using weak PMOS transistors. Port A Wake-up If the HALT instruction is executed, the device will enter the Power Down Mode, where the system clock will stop resulting in power being conserved, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the PA0~PA7 pins from high to low. After a HALT instruction forces the microcontroller into entering the Power Down Mode, the processor will remain idle or in a low-power state until the logic condition of the selected wake-up pin on Port A changes from high to low. This function is especially suitable for applications that can be woken up via external switches. Note that pins PA0 to PA7 can be selected individually to have this wake-up feature using an PA wake up option, located in the configuration. I/O Port Control Registers Each I/O port have their own control register, known as PAC, PAB, PCC and PDC, which control the input/output configuration. With this control register, each PA~PD I/O pin with or without pull-high resistors can be reconfigured by pull-hi option control. Pins PA~PD ports are directly mapped to a bit in its associated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a 1. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a 0, the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin.
* Pin-shared Functions
The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be overcome. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application program control.
* External Interrupt Input
The external interrupt pin, INT, is pin-shared with the I/O pin PA5. To use the pin as an external interrupt input the correct bits in the PA share pin option must be selected. The pin must also be setup as an input by setting the appropriate bit in the Port Control Register. A pull-high resistor can also be selected via the appropriate port pull-high option.
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* CR/F analog switch Inputs
Programming Considerations Within the user program, one of the first things to consider is port initialization. After a reset, the PA~PD data register and PAC~PDC port control register will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the PAC port control register, is then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated PA port data register is first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct value into the port control register or by programming individual bits in the port control register using the SET [m].i and CLR [m].i instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports.
T1 S y s te m C lo c k T2 T3 T4 T1 T2 T3 T4
The HT37Q70/60/50/40/30 have 8 CR/F converter inputs. All of these analog inputs are pin-shared with PC0 to PC7. If these pins are to be used as CR/F analog switch Inputs and not as normal I/O pins then the www..com corresponding bits in the Option, PC0~7 share pin configuration. The HT37Q20 have 4 CR/F converter inputs. All of these analog inputs are pin-shared with PC0 to PC3. If these pins are to be used as CR/F analog switch Inputs and not as normal I/O pins then the corresponding bits in the configuration, PC0~3 share pin configuration.
* CR/F oscillator pin
The HT37Q70/60/50/40/30/20 have 4 CR/F oscillator pins. All of these CR/F oscillator pin are pin-shared with PD0 to PD3. If these pins are to be used as CR/F oscillator pins and not as normal I/O pins then the corresponding bits in the Option, PD0~3 share pin Option. I/O Pin Structures The diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins.
P o rt D a ta
W r ite to P o r t
R e a d fro m
P o rt
Read/Write Timing
D a ta B u s W r ite C o n tr o l R e g is te r C h ip R e s e t R e a d C o n tr o l R e g is te r
C o n tr o l B it Q D V V CK S Q
DD
DD
W eak P u ll- u p M a s k O p tio n
D a ta B it Q D CK S Q M
I/O
L in e
W r ite I/O
R e a d I/O S y s te m W a k e -U p M a s k O p tio n
U X
Input/Output Port
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Timer/Event Counters
The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The devices contain two count-up timers 8-bit capacity and one count-up timers www..com 16-bit capacity. As the timer 0/1 has three different operating modes, they can be configured to operate as a general timer, an external event counter or as a pulse width measurement device. But the timer 2 only be configured to operate as a general timer. The provision of an internal prescaler to the clock circuitry of some of the timer/event counters gives added range to the timer 1/2. There are three types of registers related to the Timer/Event Counters 0. The first two register contain the actual high and low byte value of the timer and into which an initial value can be preloaded. There are two types of registers related to the Timer/Event Counters 1/2. The first is the register that contains the actual value of the timer and into which an initial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the Timer Control Register which defines the timer options and determines how the timer is to be used. The Timer/Event Counter 0 can have the timer clock configured to come from the internal clock source. The clock source is fOSC/8.In addition, the timer clock source of Timer/Event Counter 0 can also be configured to come from an internal RC 12kHz. An external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer pin, known as TMR0 or TMR1. These external timer pins are pin-shared with other I/O pins. Depending upon the condition of PA share pin option, each high to low, or low to high transition on the external timer input pin will increment the counter by one.
D a ta B u s L o w B y te B u ffe r
fO
SC
/8
M U
T0M 1 X
T0M 0
1 6 - b it T im e r /E v e n t C o u n te r P r e lo a d R e g is te r
R e lo a d
R C 12K T0S
T im e r /E v e n t C o u n te r M o d e C o n tro l
H ig h B y te T0O N
Low
B y te
TM R0
T0E
1 6 - B it T im e r /E v e n t C o u n te r
O v e r flo w to In te rru p t
16-bit Timer/Event Counter 0 Structure
D a ta B u s P r e lo a d R e g is te r T1M 1 T1PSC 2~T1PSC 0 (1 /1 6 ~ 1 /2 0 4 8 ) fO
SC
R e lo a d
T1M 0 T im e r /E v e n t C o u n te r T1O N O v e r flo w to In te rru p t
8 - S ta g e P r e s c a le r
TM R1
T1E
T im e r /E v e n t C o u n te r M o d e C o n tro l
8-bit Timer/Event Counter 1 Structure
D a ta B u s P r e lo a d R e g is te r T2M 1 T2PSC 2~T2PSC 0 (1 /1 6 ~ 1 /2 0 4 8 ) fO
SC
R e lo a d
T2M 0 T im e r C o u n te r T2O N O v e r flo w to In te rru p t
8 - S ta g e P r e s c a le r
T im e r C o u n te r M o d e C o n tro l
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Configuring the Timer/Event Counter Input Clock Source The internal timers clock can originate from various sources, depending upon timer is chosen. The system clock input timer source is used when the timer is in the www..com mode or in the pulse width measurement mode. timer For Timer/Event Counter 0, these system clock timer source is selected by TMR0C.5. For Timer/Event Counter 1, 2 this system clock timer source is first divided by a prescaler, the division ratio of which is conditioned by the Timer Control Register bits T1PSC0~T1PSC2. An external clock source is used when the timer is in the event counting mode, the clock source being provided on the external timer pin, known as TMR0 or TMR1. These external timer pins are pin-shared with other I/O pins. Depending upon the condition of PA share pin option, each high to low, or low to high transition on the external timer input pin will increment the counter by one. Timer Registers - TMR0H/TMR0L, TMR1, TMR2 The timer registers are special function registers located in the special purpose Data Memory and is the place where the actual timer value is stored. For the 8-bit timer, this register is known as Timer/Event Counter 1/2. In the case of the 16-bit timer, a pair of 8-bit registers are required to store the 16-bit timer values. These are known as TMR1L/TMR1H. The value in the timer registers increases by one each time an internal clock pulse is received or an external transition occurs on the external timer pin. The timer will count from the initial value loaded by the preload register to the full count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, at which point the timer overflows and a timer internal interrupt signal is generated. The timer value will then be reset with the initial preload register value and continue counting. Note that to achieve a maximum full range count of FFH for the 8-bit timer or FFFFH for the 16-bit timers, the preload registers must first be cleared to all zeros. It should be noted that after power-on, the preload registers will be in an unknown condition. Note that if the Timer/Event Counters are in an OFF condition and data is written to their preload registers, this data will be immediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload data register during this period will remain in the preload register and will only be written into the actual counter the next time an overflow occurs. Note also that when the timer registers are read, the timer clock will be blocked to avoid errors, however, as this may result in certain timing errors, programmers must take this into account. The 16-bit Timer/Event Counter have contained both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte register, namely TMR0L, the data will only be placed in a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMR0H, is executed. On the other hand, using instructions to preload data into the high byte timer register will result in the data being directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the
b7 T0M 1 T0M 0 T0S T0O N T0E
b0 TM R0C R e g is te r N o t im p le m e n te d , r e a d a s " 0 " E ventC 1:coun 0:coun P u ls e W 1 : s ta rt 0 : s ta rt o u n te r A c tiv e E d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g e S e le c t t A c tiv e E d g e S e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le T im e r C lo c k S o u r c e 1:R C 12K 0 : fO S C /8 O p e r a tin g M o d e S e le c T0M 0 T0M 1 no 0 0 ev 1 0 tim 0 1 pu 1 1 t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter 0 Control Register
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b7 T1M 1 T1M 0 T1O N T1E b0 T1PSC2 T1PSC1 T1PSC0 TM R 1C R e g is te r
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T im e r P r e s c a le r R a te S e le c t T 1 P S C 2 T 1 P S C 1 T 1 P S C 0 T im e r 1 :1 0 0 0 1 :3 1 0 0 1 :6 0 1 0 1 :1 1 1 0 1 :2 0 0 1 1 :5 1 0 1 1 :1 0 1 1 1 :2 1 1 1 6 2 E ventC 1:coun 0:coun P u ls e W 1 : s ta rt 0 : s ta rt o u n te r A c tiv e E d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g e S e le c t
R a te 4 28 56 12 024 048
t A c tiv e E d g e S e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r /E v e n t C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c T1M 0 T1M 1 no 0 0 ev 1 0 tim 0 1 1 1 pu t m od entc erm ls e w e a v a ila b le o u n te r m o d e ode id th m e a s u r e m e n t m o d e
Timer/Event Counter 1 Control Register
b7 T2M 1 T2M 0 T2O N T2E
b0 T2PSC 2 T2PSC 1 T2PSC 0 TM R2C R e g is te r
T im e r P r e s c a le r R a te S e le c t T 2 P S C 2 T 2 P S C 1 T 2 P S C 0 T im e r 1 :1 0 0 0 1 :3 1 0 0 1 :6 0 1 0 1 :1 1 1 0 1 :2 0 0 1 1 :5 1 0 1 1 :1 0 1 1 1 :2 1 1 1 6 2 Ev 1: 0: Pu 1: 0: entC coun coun ls e W s ta rt s ta rt o u n te r A c tiv e E d g t o n fa llin g e d g e t o n r is in g e d g e id th M e a s u r e m e n c o u n tin g o n r is in g c o u n tin g o n fa llin g e S e le c t
R a te 4 28 56 12 024 048
t A c tiv e E d g e S e le c t e d g e , s to p o n fa llin g e d g e e d g e , s to p o n r is in g e d g e
T im e r C o u n te r C o u n tin g E n a b le 1 : e n a b le 0 : d is a b le N o t im p le m e n te d , r e a d a s " 0 " O p e r a tin g M o d e S e le c T2M 0 T2M 1 no 0 0 no 1 0 tim 0 1 1 1 no t m od m od erm m od e a v a ila b le e a v a ila b le ode e a v a ila b le
Timer Counter 2 Control Register
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high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register will only result in reading the previously www..com latched contents of the low byte buffer and not the actual contents of the low byte timer register. Timer Control Registers - TMR0C, TMR1C, TMR2C The Timer/Event Counters0/1 enable them to operate in three different modes. the options of which are determined by the contents of their respective control register. There are four timer control registers, known as TMR0C, TMR1C and TMR2C. It is the timer control register together with its corresponding timer registers that control the full operation of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialization. To choose which of the three modes the timer is to operate in, either in the timer mode, the event counting mode or the pulse width measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair T0M1/T0M0, T1M1/T1M0 respectively, depending upon which timer is used, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as T0ON, T1ON or T2ON, depending upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. If the timer is in the event count or pulse width measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as T0E, T1E or T2E, depending upon which timer is used. Configuring the Timer Mode In this mode, the timer can be utilized to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, bits TM1 and TM0 of the TMR0C~TMR2C register must be set to 1 and 0 respectively. In this mode, the internal clock is used as the timer clock. The input clock frequency of 16 bit timer to the timer is fOSC/8 and RC12K, selected by TMR0C.5. The input clock frequency of 8 bit timer to the timer is Fosc divided by the value programmed into the timer prescaler, the value of which is determined by bits PSC0~PSC2 of the TMR1C~ TMR2C register. The timer-on bit, TON must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one. When the timer is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ET0I~ET2I bit in the INTC and INTCH registers is cleared to zero. It should be noted that a timer overflow is one of the wake-up sources. Configuring the Event Counter Mode In this mode, two number of externally changing logic events, occurring on external pin PA6/TMR0 or PA7/TMR1, can be recorded by the internal timer. For the timer to operate in the event counting mode, bits TM1 and TM0 of the TMR0C or TMR1C registers must be set to 0 and 1 respectively. The timer-on bit, TON must be set high to enable the timer to count. With TE low, the counter will increment each time the PA6/TMR0 or PA7/TMR1 pin receives a low to high transition. If the TE bit is high, the counter will increment each time PA6/TMR0 or PA7/TMR1 pin receives a high to low transition. As in the case of the other two modes, when the counter is full and overflows, the timer will be reset to the value already loaded into the preload register and continue counting. If the timer interrupt is enabled, an interrupt signal will also be generated. The timer interrupt can be disabled by ensuring that the ETI bit in the INTC and INTCH registers is cleared to zero. To ensure that the external pin PA6/TMR0 or PA7/TMR1 is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the TM0 and TM1 bits place the timer/event counter in the event counting mode, the second is to ensure that the share pin MR0 or TMR1 are selected by option. It should be noted that a timer overflow is one of the wake-up sources. Also in the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. As a result when the timer overflows it will generate a wake-up and if the interrupts are enabled also generate a timer interrupt signal.
P r e s c a le r O u tp u t In c re m e n t T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
T im e r + N
T im e r + N
+1
Timer Mode Timing Diagram
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E x te r n a l T im e r P in In p u t T0E orT1E=1
In c re m e n t T im e r C o u n te r
T im e r + 1
T im e r + 2
T im e r + 3
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Event Counter Mode Timing Diagram
Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA6/TMR0 or PA7/TMR1 can be measured. In the Pulse Width Measurement Mode, the timer clock source is supplied by the internal clock. For the timer to operate in this mode, bits TM0 and TM1 must both be set high. If the TE bit is low, once a high to low transition has been received on the PA6/TMR0 or PA7/TMR1 pin, the timer will start counting until the PA6/TMR0 or PA7/TMR1 pin returns to its original high level. At this point the TON bit will be automatically reset to zero and the timer will stop counting. If the TE bit is high, the timer will begin counting once a low to high transition has been received on the PA6/TMR0 or PA7/TMR1 pin and stop counting when the PA6/TMR0 or PA7/TMR1 pin returns to its original low level. As before, the TON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the TON bit is automatically reset to zero when the external control signal on the external timer pin returns to its original level, whereas in the other two modes the TON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore represents the length of the pulse received on pin PA6/TMR0 or PA7/TMR1. As the TON bit has now been reset any further transitions on the PA6/TMR0 or PA7/TMR1 pin will be ignored. Not until the TON bit is again set high by the program can the timer begin further pulse width measurements. In this way single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logical transitions on the PA6/TMR0 or PA7/TMR1 pin and not by the logic level.
Prescaler Bits PSC0~PSC2 of the TMRC1~ TMRC2 registers can be used to define the pre-scaling stages of the internal clock sources of the Timer/Event Counter. Note: Because the two timers are used by MIDI the external timer pin functions are disabled. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, require the use of the external PA6/TMR0 or PA7/TMR1 pin for correct operation. As this pin is a shared pin it must be configured correctly to ensure it is setup for use as a Timer/Event Counter input and not as a normal I/O pin. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the PA share pin option must be selected to ensure that the pin is setup as an TMR0 and TMR1 input. Programming Considerations When configured to run in the timer mode, the internal system clock fOSC/8 is used as the timer clock source and is therefore synchronized with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an internal interrupt signal directing the program flow to the respective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external timer input pin. As this is an external event and not synch r o n i ze d w i t h t h e i n t e r n a l t i m e r cl o ck, t h e microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be
E x te r n a l T im e r P in In p u t TON ( w ith T E = 0 ) P r e s c a le r O u tp u t In c re m e n t T im e r C o u n te r T im e r +1 +2 +3
SC
+4 /8 o r R C 1 2 K .
P r e s c a le r O u tp u t is s a m p le d a t e v e r y fa llin g e d g e o f fO
Pulse Width Measure Mode Timing Diagram
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small differences in measured values requiring programmers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronized with the internal system or timer clock. www..com When the Timer/Event Counter is read, or if data is written to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly initialized before using them for the first time. The associated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control register must also be correctly set to ensure the timer is properly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer registers are unknown. After the timer has been initialized the timer can be turned on and off by controlling the enable bit in the timer control Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the interrupts are enabled and managed. Note how the Timer/Event Counter is turned on, by setting bit 4 of the Timer Control Register. The Timer/Event Counter can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter to be in the timer mode, which uses the internal system clock as the clock source. Show how to counter TMR0=1kHz, TMR1=2kHz, TMR2=4kHz, if fOSC is 11.059MHz. org 00h ; Reset jmp begin org 04h ; external interrupt vector reti org 08h ; Timer/Event Counter 0 interrupt vector jmp tmr0int ; jump here when Timer0 overflows org 0ch ; Timer/Event Counter 1 interrupt vector jmp tmr1int ; jump here when Timer1 overflows org 10h ; Timer Counter 2 interrupt vector jmp tmr2int ; jump here when Timer2 overflows org 20h ; main program ;internal Timer0,1,2 Counter interrupt routine tmr0int: ; Timer/Event Counter 0 main program placed here : reti tmr1int: ; Timer/Event Counter 1 main program placed here : reti tmr2int: ; Timer Counter 2 main program placed here : reti : begin: ; setup interrupt register Rev. 1.00 34 February 17, 2009 register. Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer operation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corresponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irrespective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condition. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these external events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt request flag should first be set high before issuing the HALT instruction to enter the Power Down Mode.
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mov mov mov mov a, 0bh intc,a a, 01h intch,a ; enable master interrupt, timer0 and timer1 interrupt ; enable timer2 interrupt
;setup Timer 0 registers www..coma, low (65536-1382) mov mov TMR0L,a; mov a, high (65536-1382) mov TMR0H,a; mov a,080h mov tmr0c,a set tmr0c.4 mov mov mov mov set mov mov mov mov set a, low (256-173) TMR1,a; a,080h tmr1c,a tmr1c.4 a, low (256-173) TMR2,a; a,080h tmr2c,a tmr2c.4
; setup Timer preload low byte value, interrupt in 1kHz ; setup Timer preload high byte value ; setup Timer 0 control register ; timer mode and clock source is fOSC/8 (R) 0.7234ms ; start Timer - note mode bits must be previously setup ; setup Timer preload value, interrupt in 2kHz ; setup Timer 1control register ; timer mode and Prescaler output is fOSC/32 (R) 2.89ms ; start Timer - note mode bits must be previously setup ; setup Timer preload value, interrupt in 4kHz ; setup Timer2 control register ; timer mode and Prescaler output is fOSC/16 (R) 1.447ms ; start Timer - note mode bits must be previously setup
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter 0/1/2 or ERCOCI require or an ADPCM empty requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. Each device in this series contains a single external interrupt and two internal interrupts functions. The external interrupt is controlled by the action of the external INT pin, while the internal interrupts are controlled by the Timer/Event 0/1Counter overflow or ERCOCI require or the ADPCM empty interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by INTC and INTCH registers, which are located in Data Memory. By controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation Timer/Event 0/1/2 Counter overflow, ERCOCI interrupt, ADPCM empty request or the external interrupt line being pulled low will all generate an interrupt request by setting their corresponding request flag, if their appropriate interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred.
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Once an interrupt subroutine is serviced, all the other interrupts will be blocked, as the EMI bit will be cleared automatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests occur durwww..com ing this interval, although the interrupt will not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the routine, to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. In cases where both external and internal interrupts are enabled and where an external and internal interrupt occurs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC register can prevent simultaneous occurrences. Interrupt Source Reset External Interrupt Timer/Event Counter 0 Overflow Timer/Event Counter 1 Overflow Timer Counter 2 overflow ERCOCI Interrupt ADPCM Empty Interrupt External Interrupt For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit, EEI, must first be set. An actual external interrupt will take place when the external interrupt request flag, EIF, is set, a situation that will occur when a high to low transition appears on the INT line. The external interrupt pin is pin-shared with the I/O pin PA5 and can only be configured as an external interrupt pin if the corresponding external interrupt enable bit in the INTC register has been set. The pin must also be selected as by setting the corresponding PAC.5 bit in the port control register. When the interrupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subroutine call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the external interrupt request flag, EIF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Priority 1 2 3 4 5 6 7 Vector 00H 04H 08H 0CH 10H 14H 18H
b7 T1F T0F E IF ET1I ET0I EEI
b0 EMI IN T C R e g is te r M a s te r In te r r u p t G lo b a l E n a b le 1 : g lo b a l e n a b le 0 : g lo b a l d is a b le E x te r n a l In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 0 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le T im e r /E v e n t C o u n te r 1 In te r r u p t E n a b le 1 : e n a b le 0 : d is a b le E x te r n a l In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e N o im p le m e n te d , r e a d a s " 0 "
Interrupt Low Byte Control Register
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b7 CH1F AD PCM F RCOCF T2F CH0F EADPCM b0 E R C O C I E T 2 I IN T C H R e g is te r
T im e r C o u n te r 2 In te r r u p t E n a b le 1 : e n a b le d 0 : d is a b le d
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C /R to F In te r r u p t E n a b le 1 : e n a b le d 0 : d is a b le d A D P C M E m p ty In te r r u p t E n a b le 1 : e n a b le d 0 : d is a b le d A D P C M C h a n n e l 0 E m p ty In te r r u p t R e q u e s t F la g 1 : e n a b le d 0 : d is a b le d T im e r C o u n te r 2 In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e C /R to F In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e A D P C M E m p ty In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e A D P C M C h a n n e l 1 E m p ty In te r r u p t R e q u e s t F la g 1 : a c tiv e 0 : in a c tiv e
Interrupt High Byte Control Register
A u to m a tic a lly C le a r e d b y IS R M a n u a lly S e t o r C le a r e d b y S o ftw a r e E x te rn a l In te rru p t R e q u e s t F la g E IF T im e r /E v e n t C o u n te r 0 In te r r u p t R e q u e s t F la g T 0 F T im e r /E v e n t C o u n te r 1 In te r r u p t R e q u e s t F la g T 1 F T im e r C o u n te r 2 In te r r u p t R e q u e s t F la g T 2 F C /R to F (E R C O C I) In te r r u p t R e q u e s t F la g R C O C F A D P C M E m p ty In te rru p t R e q u e s t F la g A D P C M F EEI
A u to m a tic a lly D is a b le d b y IS R C a n b e E n a b le d M a n u a lly P r io r ity EMI H ig h
ET0I
ET1I In te rru p t P o llin g
ET2I
RCOCF Low
EADPCM
Interrupt Structure
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Timer/Event Counter Interrupts For a timer generated internal interrupt to occur, the corresponding internal interrupt enable bit must be first set. Each device have two internal Timer Counters, the Timer/Event Counter 0 interrupt enable is bit 2 of the www..com register and known as ET0I, the Timer/Event INTC Counter 1 interrupt enable is bit 3 of the INTC register and known as ET1I and the Timer Counter 2 interrupt enable is bit 0 of the INTCH register and is known as ET2I. An actual Timer/Event Counter interrupt will be initialized when the Timer/Event Counter interrupt request flag is set, caused by a timer overflow. Each device has two timers, the Timer/Event Counter 0 request flag is bit 5 of the INTC register and known as T0F, the Timer/Event Counter 1 request flag is bit 6 of the INTC register and known as T1F, and the Timer Counter 2 request flag is bit 4 of the INTCH register and is known as T2F. When the master interrupt global enable bit is set, the stack is not full and the corresponding timer interrupt enable bit is set, an internal interrupt will be generated when the corresponding timer overflows. Each device have two internal Timer/Event Counters, a subroutine call to location 08H will occur for Timer/Event Counter 0, a subroutine call to location 0CH for Timer/Event Counter 1, a subroutine call to location 10H for Timer Counter 2. After entering the timer interrupt execution routine, the corresponding timer interrupt request flag, either, T0F, T1F or T2F will be reset and the EMI bit will be cleared to disable other interrupts. RC/F Interrupt The external RC Oscillation Converter interrupt is initialized by setting the external RC Oscillation Converter interrupt request flag, RCOCF; bit 5 of INTCH. This is caused by a Timer A or Timer B overflow. When the interrupt is enabled, and the stack is not full and the RCOCF bit is set, a subroutine call to location 14H will occur. The related interrupt request flag, RCOCF, will be reset and the EMI bit cleared to disable further interrupts. ADPCM Interrupt The internal ADPCM interrupt is initialized by setting the ADPCM interrupt request flag (ADPCMF: bit 6, CH0F: bit 3 and CH1F: bit 7 of INTCH).The CH0F and CH1F set by ADR0 or ADR1 empty respectively. The ADPCMF is set by ADR0 or ADR1 empty immediately. When the interrupt is enabled, and the stack is not full and the T0F bit is set, a subroutine call to location 18H will occur. The related interrupt request ADPCMF and CH0F/CH1F flag will be reset and the EMI bit cleared to disable further interrupts. Programming Considerations The interrupt request flags T0F, T1F, T2F, ADPCMF, CH0F, CH1F, together with the interrupt enable bits ET0I, ET1I, ET2I, EADPCM, form the interrupt control registers INTC, INTCH which are located in the Data Memory. By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC or INTCH register until the corresponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the CALL subroutine instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance.
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Reset and Initialisation
A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after www..com power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, after a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is forcefully pulled low. In such a case, known as a normal operation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of reset operations result in different register conditions being setup. Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RES reset is implemented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and externally:
* Power-on Reset
to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer.
VDD RES S S T T im e - o u t In te rn a l R e s e t 0 .9 V tR
DD
STD
Power-On Reset Timing Chart For most applications a resistor connected between VDD and the RES pin and a capacitor connected between VSS and the RES pin will provide a suitable external reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference.
VDD 100kW RES 0 .1 m F VSS
Basic Reset Circuit For applications that operate within an environment where more noise is present the Enhanced Reset Circuit shown is recommended.
0 .0 1 m F 100kW RES
10kW
VDD
The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory address, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recommended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period
0 .1 m F VSS
Enhanced Reset Circuit More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website.
* RES Pin Reset
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initiated from this point.
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RES S S T T im e - o u t In te rn a l R e s e t 0 .4 V 0 .9 V
DD DD
Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF 0 u 0 1 1 0 u 1 u 1 RESET Conditions RES reset during power-on RES or LVR reset during normal operation RES Wake-up HALT WDT time-out reset during normal operation WDT time-out reset during Power Down
tR
STD
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RES Reset Timing Chart
* Low Voltage Reset - LVR
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device, which is selected via a configuration option and The VLVR can select as 3.3V or 2.2V. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: For a valid LVR signal, a low voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for greater than the value tLVR specified in the A.C. characteristics. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
LVR tR S S T T im e - o u t In te rn a l R e s e t
STD
Note: u stands for unchanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Program Counter Interrupts WDT Timer/Event Counter Prescaler Condition After RESET Reset to zero All interrupts will be disabled Clear after reset, WDT begins counting Timer Counter will be turned off The Timer Counter Prescaler will be cleared
Low Voltage Reset Timing Chart
* Watchdog Time-out Reset during Normal Operation
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to 1.
W D T T im e - o u t
Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack
tR
S S T T im e - o u t In te rn a l R e s e t
STD
WDT Time-out Reset during Normal Operation Timing Chart
* Watchdog Time-out Reset during Power Down
The different kinds of resets all affect the internal registers of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers.
The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and the TO flag will be set to 1. Refer to the A.C. Characteristics for tSST details.
W D T T im e - o u t
tS
S S T T im e - o u t
ST
WDT Time-out Reset during Power Down Timing Chart Rev. 1.00 40 February 17, 2009
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HT37Q70/60 Register TMR0H TMR0L www..com TMR0C TMR1L TMR1C TMR2L TMR2C PCL MP0 MP1 MP2 RBP1 RBP2 BP1 ACC TBLP1 TBLH TBMP1 TBHP1 STATUS INTC INTCH PA PAC PB PBC PC PCC PD PDC DACC DAH DAL CHAN FreqNH FreqNL AddrH AddrL RepH RepL ENV Reset (Power-on) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx
---- ---0 ---- ---0
RES or LVR Reset xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (HALT) uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---u ---- ---u
xxx0 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 xxxx xxxx xxxx xxxx 00-- --00 xxxx xxxx xxxx xxxx --xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx x--- xxxx
xxx0 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
xxx0 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
xxx0 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu uuuu u-uu uuuu uuuu uuuu uuuu uu-- --uu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
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Register RVC WDTS ADR www..com XSPL XSPH ADPC ADPS ASCR TMRAH TMRAL RCOCCR TMRBH TMRBL RCOCR Reset (Power-on) xxxx xxxx 0000 0111 xxxx xxxx 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 RES or LVR Reset uuuu uuuu 0000 0111 xxxx xxxx 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (Normal Operation) uuuu uuuu 0000 0111 xxxx xxxx 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (HALT) uuuu uuuu 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u --uu ---- uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu ---- --uu
Note: u stands for unchanged x stands for unknown - stands for unimplemented
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HT37Q50/40 Register TMR0H TMR0L www..com TMR0C TMR1L TMR1C TMR2L TMR2C PCL MP0 MP1 MP2 RBP1 RBP2 BP1 ACC TBLP1 TBLH TBMP1 TBHP1 STATUS INTC INTCH PA PAC PB PBC PC PCC PD PDC DACC DAH DAL CHAN FreqNH FreqNL AddrH AddrL RepH RepL ENV Reset (Power-on) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx
---- ---0 ---- ---0
RES or LVR Reset xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (HALT) uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---u ---- ---u
xxxx 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 xxxx xxxx xxxx xxxx 00-- --00 xxxx xxxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx x--- xxxx
xxxx 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
xxxx 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
xxxx 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu uuuu u-uu uuuu uuuu uuuu uuuu uu-- --uu uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu
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Register RVC WDTS ADR www..com XSPL XSPH ADPC ADPS ACSR ADRL ADRH ADCR ASCR TMRAH TMRAL RCOCCR TMRBH TMRBL RCOCR Reset (Power-on) xxxx xxxx 0000 0111 xxxx xxxx 0000 0000 0000 0000 00-0 --00 ---- 1111 1--- --00 xxxx ---xxxx xxxx 0100 0000 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 RES or LVR Reset uuuu uuuu 0000 0111 xxxx xxxx 0000 0000 0000 0000 00-0 --00 ---- 1111 1--- --00 xxxx ---xxxx xxxx 0100 0000 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (Normal Operation) uuuu uuuu 0000 0111 xxxx xxxx 0000 0000 0000 0000 00-0 --00 ---- 1111 1--- --00 xxxx ---xxxx xxxx 0100 0000 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (HALT) uuuu uuuu 0000 0uuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u --uu ---- uuuu 1--- --uu uuuu ---uuuu uuuu u1uu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu ---- --uu
Note: u stands for unchanged x stands for unknown - stands for unimplemented
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HT37Q30 Register TMR0H TMR0L www..com TMR0C TMR1L TMR1C TMR2L TMR2C PCL MP0 MP1 MP2 RBP1 RBP2 BP1 ACC TBLP1 TBLH TBMP1 STATUS INTC INTCH PA PAC PC PCC PD PDC DACC DAH DAL CHAN FreqNH FreqNL AddrH AddrL RepH RepL ENV RVC WDTS ADR Reset (Power-on) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx
---- ---0 ---- ---0
RES or LVR Reset xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (HALT) uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---u ---- ---u
xxxx x000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 xxxx xxxx xxxx xxxx 00-- --00 xxxx xxxx xxxx xxxx ---- xxxx xxxx xxxx xxxx xxxx xxxx xxxx x--- xxxx xxxx xxxx 0000 0111 xxxx xxxx
xxxx x000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu uuuu uuuu 0000 0111 xxxx xxxx
xxxx x000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 1000 1000 1111 1111 1111 1111 1111 1111 1111 1111 ---- 1111 ---- 1111 0000 0-00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu uuuu uuuu 0000 0111 xxxx xxxx
xxxx x000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu uuuu u-uu uuuu uuuu uuuu uuuu uu-- --uu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu uuuu uuuu 0000 0uuu uuuu uuuu
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Register XSPL XSPH ADPC www..com ADPS ASCR TMRAH TMRAL RCOCCR TMRBH TMRBL RCOCR Reset (Power-on) 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 RES or LVR Reset 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (Normal Operation) 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- 0000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (HALT) uuuu uuuu uuuu uuuu uu-u --uu ---- uuuu ---- uuuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu ---- --uu
Note: u stands for unchanged x stands for unknown - stands for unimplemented
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HT37Q20 Register TMR0H TMR0L www..com TMR0C TMR1L TMR1C TMR2L TMR2C PCL MP0 MP1 MP2 RBP1 RBP2 BP1 ACC TBLP1 TBLH TBMP1 STATUS INTC INTCH PA PAC PC PCC PD PDC DACC DAH DAL CHAN FreqNH FreqNL AddrH AddrL RepH RepL ENV RVC WDTS ADR Reset (Power-on) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx
---- ---0 ---- ---0
RES or LVR Reset xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (Normal Operation) xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx 00-0 1000 xxxx xxxx 00-0 1000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---0 ---- ---0
WDT Time-out (HALT) uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uu-u uuuu uuuu uuuu uu-u uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu
---- ---u ---- ---u
xxxx xx00 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --00 xxxx -000 0000 1000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- 1111 ---- 1111 000- --00 xxxx xxxx xxxx xxxx 00-- --00 xxxx xxxx xxxx xxxx ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx x--- xxxx xxxx xxxx 0000 0111 xxxx xxxx
xxxx xx00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu -000 0000 1000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- 1111 ---- 1111 000- --00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu uuuu uuuu 0000 0111 xxxx xxxx
xxxx xx00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --1u uuuu -000 0000 1000 1000 1111 1111 1111 1111 ---- 1111 ---- 1111 ---- 1111 ---- 1111 000- --00 uuuu uuuu uuuu uuuu 00-- --00 uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu uuuu uuuu 0000 0111 xxxx xxxx
xxxx xx00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --11 uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu ---- uuuu ---- uuuu ---- uuuu uuu- --uu uuuu uuuu uuuu uuuu u u - - - -u u uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu u--- uuuu uuuu uuuu 0000 0uuu uuuu uuuu
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Register XSPL XSPH ADPC www..com ADPS ASCR TMRAH TMRAL RCOCCR TMRBH TMRBL RCOCR Reset (Power-on) 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 RES or LVR Reset 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (Normal Operation) 0000 0000 0000 0000 00-0 --00 ---- 1111 ---- -000 xxxx xxxx xxxx xxxx 0000 1--xxxx xxxx xxxx xxxx ---- --00 WDT Time-out (HALT) uuuu uuuu uuuu uuuu uu-u --uu ---- uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu u--uuuu uuuu uuuu uuuu ---- --uu
Note: u stands for unchanged x stands for unknown - stands for unimplemented
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Oscillator
Various oscillator options offer the user a wide range of functions according to their various application requirements. Two types of system clocks can be selected while various clock source options for the Watchdog www..com Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. The two methods of generating the system clock are:
* External crystal/resonator oscillator * External RC oscillator
with the crystal or resonator manufacturers specification. The external parallel feedback resistor, Rp, is normally not required but in some cases may be needed to assist with oscillation start up. Internal Ca, Cb, Rf Typical Values @ 5V, 25C Ca 7pF~9pF Cb 9pF~11pF Rf 300kW
Oscillator Internal Component Values External RC Oscillator Using the external system RC oscillator requires that a resistor, with a value between 82kW and 180kW, is connected between OSC1 and VSS. The generated system clock divided by 8 will be provided on OSC2 as an output which can be used for external synchronization purposes. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be connected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, temperature and process variations and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are required. For the value of the external resistor. Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation.
OSC1 R fO
SC OSC
One of these two methods must be selected using the configuration options. More information regarding the oscillator is located in Application Note HA0075E on the Holtek website. External Crystal/Resonator Oscillator The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, and will normally not require external capacitors. However, for some crystals and most resonator types, to ensure oscillation and accurate frequency generation, it may be necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation
C1 Rp In te r n a l O s c illa to r C ir c u it
OSC1 Rf Ca
Cb C2 OSC2
T o in te r n a l c ir c u its
N o te : 1 . R p is n o r m a lly n o t r e q u ir e d . 2 . A lth o u g h n o t s h o w n O S C 1 /O S C 2 p in s h a v e a p a r a s itic c a p a c ita n c e o f a r o u n d 7 p F .
/8 N M O S O p e n D r a in
OSC2
Crystal/Resonator Oscillator External RC Oscillator
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Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65ms at 5V requiring no external components. When the device enters the Power Down Mode, the system clock will stop www..com but the WDT oscillator continues to free-run and running to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have different package types, as there may be undonbed pins, which must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have enabled the Watchdog Timer internal oscillator. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows:
* An external reset * An external falling edge on Port A * A system interrupt * A WDT overflow
Power Down Mode and Wake-up
Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode, also known as the HALT Mode or Sleep Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs because when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the HALT instruction in the application program. When this instruction is executed, the following will occur:
* The system oscillator will stop running and the appli-
cation program will stop at the HALT instruction.
* The Data Memory contents and registers will maintain
If the system is woken up by an external reset, the device will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the actual source of the wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the HALT instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual configuration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up occurs, the program will resume execution at the instruction following the HALT instruction. If the system is woken up by an interrupt, then two possible situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the HALT instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to 1 before entering the Power Down Mode, the wake-up function of the related interrupt will be disabled.
their present condition.
* The WDT will be cleared and resume counting if the
WDT clock source is selected to come from the WDT oscillator. The WDT will stop if its clock source originates from the system clock.
* The I/O ports will maintain their present condition. * In the status register, the Power Down flag, PDF, will
be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of the MCU to as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimized. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either
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No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal system operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt subroutine www..com execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the HALT instruction, this will be executed immediately after the 1024 system clock period delay has ended. source instead of the internal WDT oscillator. If the instruction clock is used as the clock source, it must be noted that when the system enters the Power Down Mode, as the system clock is stopped, then the WDT clock source will also be stopped. Therefore the WDT will lose its protecting purposes. In such cases the system cannot be restarted by the WDT and can only be restarted using external signals. For systems that operate in noisy environments, using the internal WDT oscillator is therefore the recommended choice. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. However, if the system is in the Power Down Mode, when a WDT time-out occurs, only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT and the WDT prescaler. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instructions and the third is via a HALT instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the single CLR WDT instruction while the second is to use the two commands CLR WDT1 and CLR WDT2. For the first option, a simple execution of CLR WDT will clear the WDT while for the second option, both CLR WDT1 and CLR WDT2 must both be executed to successfully clear the WDT. Note that for this second option, if CLR WDT1 is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a CLR WDT2 instruction will clear the WDT. Similarly, after the CLR WDT2 instruction has been executed, only a successive CLR WDT1 instruction can clear the Watchdog Timer.
Watchdog Timer
The Watchdog Timer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is supplied by one of two sources selected by configuration option: its own self contained dedicated internal WDT oscillator or fOSC/8. Note that if the WDT configuration option has been disabled, then any instruction relating to its operation will result in no operation. The internal WDT oscillator has an approximate period of 65ms at a supply voltage of 5V. If selected, it is first divided by 256 via an 8-stage counter to give a nominal period of 17ms. Note that this period can vary with VDD, temperature and process variations. For longer WDT time-out periods the WDT prescaler can be utilized. By writing the required value to bits 0, 1 and 2 of the WDTS register, known as WS0, WS1 and WS2, longer time-out periods can be achieved. With WS0, WS1 and WS2 all equal to 1, the division ratio is 1:128 which gives a maximum time-out period of about 2.1s. A configuration option can select the instruction clock, which is the system clock divided by 8, as the WDTclock
b7 W S2 W S1
b0 W S0 W D T S R e g is te r W D T p r e s c a le r r a te s e le c t W DTR W S0 W S1 W S2 1 :1 0 0 0 1 :2 1 0 0 1 :4 0 1 0 1 :8 1 1 0 1 :1 0 0 1 1 :3 1 0 1 1 :6 0 1 1 1 :1 1 1 1 2 4 N otused a te
6 28
Watchdog Timer Register
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CLR CLR W D T 1 F la g W D T 2 F la g C le a r W D T T y p e C o n fig u r a tio n O p tio n CLR W D T C lo c k S o u r c e C o n fig u r a tio n O p tio n 8 - b it C o u n te r ( 2 5 6 )
1 o r 2 In s tr u c tio n s fO
SC
/8
CLR 7 - b it P r e s c a le r
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W D T O s c illa to r W D T C lo c k S o u r c e
8 -to -1 M U X W D T T im e - o u t
W S0~W S2
Watchdog Timer
Digital to Analog Converter (DACC) The two D/A converters of HT37Q70/60/50/40/30/20 are 16-bit high-resolution with excellent frequency response characteristics and good power consumption for mono audio output. D7 1Dh 1Eh 1Fh DAC High Byte DAC Low Byte DAC Control (DACC) B15 B7 BP_R D6 B14 B6 D5 B13 B5 D4 B12 B4 D3 B11 B3 D2 B10 B2 3/4 D1 B9 B1 DAC D0 B8 B0 SELWR
SELACH1 SELACH0 AMP_M AMP_EN
Note: B15~B0 is D/A conversion result data bit MSB~LSB.
b7 BP_R SELACH 1 SELACH 0 AM P_M AM P_EN DAC
b0 SELW R
DACC
R e g is te r
m C o r w a v e ta b le
T o s e le c t D A R d a ta fr o m 0 : fr o m m C ( d e fa u lt) 1 : fr o m w a v e ta b le
E n a b le /d is a b le D A C fu n c tio n 0 : d is a b le 1 : e n a b le N o t im p le m e n te d , r e a d a s " 0 " E n a b le /d is a b le b u ild - in p o w e r A m p . fu n c tio n 0 : d is a b le 1 : e n a b le M u te fu n c tio n in th e b u ild - in p o w e r A m p . 0 : n o n -m u te 1 : m u te S e le c t c h 0 s o u r c e fr o m w a v e ta b le /A D P C M 0 : fr o m w a v e ta b le 1 : fro m A D P C M d e c o d e r S e le c t c h 0 1 s o u r c e fr o m 0 : fr o m w a v e ta b le 1 : fro m a d p c m d e c o d e r w a v e ta b le /A D P C M M P 1 /M P 2 decoder decoder
* In d ir e c t m e m o r y a c c e s s s fr o m 0:M P1 1:M P2
DACC (1FH) Register Note: *Switch MP1and MP2 memory pointer by BP_R HT37Q20 dont contain bit2, bit3 and bit4 of DACC
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The Integrated Power Amp. The Power Amp. is an integrated class AB mono speaker driver contained in HT37Q70/60/50/40/30.It provides property of high S/N ratio, high slew rate, low distortion, large output voltage swing, excellent power supply www..com ripple rejection, low power consumption, low standby current and power off control etc.
SPK RCH SP+ SP0 .1 m F R AMP1 AMP2
OUTP
SP+:Audio Negative output SP-: Audio Positive output OUTP Rising Time (tR) When AMP_EN enable, the Power Amp. need rising time to output fully on OUTP pin. However, the rising time depends on. C1. (*The C1 connects with VBIAS and Vss)
10R R
AM P_EN
A u d In C1 V
B IA S
R B IA S AM P_EN
Aud In: Audio input VBIAS: Speaker non-inverting input voltage reference
tR
Capacitor tR Voltage 2.2V 3V 4 15ms 15ms 15ms 30ms 30ms 30ms 90ms 90ms 90ms 185ms 185ms 185ms 0.1mF 1mF 4.7mF 10mF
For battery based applications, power consumption is a key issue, therefore the amplifier should be turned off when in the standby state. In order to eliminate any speaker sound bursts while turning the amplifier on, the application circuit, which will incorporate a capacitance value of C1, should be adjusted in accordance with the speaker s audio frequency response. A greater value of C1 will improve the noise burst while turning on the amplifier. The recommended operation sequence is: Turn On: audio signal standby (1/2VDD) (R) enable amplifier (R) wait tR for amplifier ready (R) audio output Turn Off: audio signal finished (R) disable amplifier (R) wait tR for amplifier off (R) audio signal off
RCH tR AM P_EN tR
If the application is not powered by batteries and there is no problem with amplifier On/Off issue, a capacitor value of 0.1mF for C1 is recommended. How to use integrated power Amp?
* Connect the Internal Power Amp Circuit, please refer to Application Circuits. * Set DACC.3 to enable integrated power amp. Clear DACC.3 to disable integrated power amp. * User can control it at PowerAmpDisable and PowerAmpEnable of HT-MDS.
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Music Synthesis Controller - MSC
CH0~CH3 Channel Number Selection Each devices with integrated 4 channels output is selected by 2bits option and CHAN[1:0] is used to define which www..com channel is selected. When this register is written to, the wavetable synthesizer will automatically output the dedicated PCM code. So this register is also used as a start playing key and it has to be written to after all the other wavetable function registers are already defined. Change Parameter Selection These two bits, VM and FR, are used to define which register will be updated on this selected channel. There are two modes that can be selected to reduce the process of setting the register. Please refer to the statements of the following table: VM 0 0 1 1 FR 0 1 0 1 Function Update all the parameter Only change the frequency parameter Only change the volume parameter Unused HT37Q70/60 contains ST13~ST0 is used to define the start address of each PCM code and reads the waveform data from this location.
* HT37Q70/60 provides PCM 12/8 bit source * PCM 12 Start address definition * PCM code has to be located at a multiple of 48 (byte) * ST12~ST0= WA18~WA0/48 * PCM 8 Start address definition * PCM code has to be located at a multiple of 32 (byte) * ST13~ST0= WA18~WA0/32
HT37Q50/40 contains ST12~ST0 is used to define the start address of each PCM code and reads the waveform data from this location.
* HT37Q50/40 provides PCM 12/8 bit source * PCM 12 Start address definition * PCM code has to be located at a multiple of 48 (byte) * ST11~ST0= WA17~WA0/48 * PCM 8 Start address definition * PCM code has to be located at a multiple of 32 (byte) * ST12~ST0= WA17~WA0/32
Output Frequency Definition The data on BL3~BL0 and FR11~FR0 are used to define the output speed of the PCM file, i.e. it can be used to generate the tone scale. When the FR11~FR0 is 800H and BL3~BL0 is 6H, each sample data of the PCM code will be sent out sequentially. When the fOSC is 11.059MHz, the formula of a tone frequency is: f / (16x8) FR11 ~ FR0 fOUT= fRECORD x osc x (17 - BL3~BL0) 2 SR where fOUT is the output signal frequency, fRECORD and SR is the frequency and sampling rate on the sample code, respectively. So if a voice code of C3 has been recorded which has the fRECORD of 261Hz and the SR of 11025Hz, the tone frequency (fOUT) of G3: fOUT=98Hz. Can be obtained by using the formula: If FR=031h and BL=7, could get 98Hz. 98Hz= 261Hz x FR11 ~ FR0 86.4kHz x 11.025kHz 2 (17 - BL3~BL0)
HT37Q30 contains ST11~ST0 is used to define the start address of each PCM code and reads the waveform data from this location.
* HT37Q30 provides PCM 12/8 bit source * PCM 12 Start address definition * PCM code has to be located at a multiple of 48 (byte) * ST10~ST0= WA16~WA0/48 * PCM 8 Start address definition * PCM code has to be located at a multiple of 32 (byte) * ST11~ST0= WA16~WA0/32
HT37Q20 contains ST10~ST0 is used to define the start address of each PCM code and reads the waveform data from this location.
* HT37Q20 provides PCM 12/8 bit source * PCM 12 Start address definition * PCM code has to be located at a multiple of 48 (byte)
BL3~BL0: range from 00h~0Bh FR11~FR0: range from 000h~3FFh Start Address Definition Each device provides two address types for extended use, one is the program ROM address which is program counter corresponding with BP1 value, the other is the start address of the PCM code.
* ST9~ST0= WA15~WA0/48 * PCM 8 Start address definition * PCM code has to be located at a multiple of 32 (byte) * ST10~ST0= WA15~WA0/32
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Waveform Format Definition Each device accepts two waveform formats to ensure a more economical data space. WBS is used to define the sample format of each PCM code. WBS=0 means the sample format is 8-bit (PCM8) www..com means the sample format is 12-bit (PCM12) WBS=1 The 12-bit sample format allocates location to each sample data. Please refer to the waveform format statement as shown below.
8 - B it 1B 2B 3B 4B 5B 6B 7B 8B
Repeat Number Definition The repeat number is used to define the address which is the repeat point of the sample. When the repeat number is defined, it will be output from the start code to the end code once and always output the range between the repeat address to the end code (80H) until the volume become close. The RE14~RE0 is used to calculate the repeat address of the PCM code. The process for setting the RE14~RE0 is to write the 2s complement of the repeat length to RE14~RE0, with the highest carry ignored. The HT37 will get the repeat address by adding the RE14~RE0 to the address of the end code, then jump to the address to repeat this range. Volume Control Each device provides the volume control independently. The volume are controlled by VR9~VR0 respectively. The chip provides 1024 levels of controllable volume, the 000H is the maximum and 3FFH is the minimum output volume. The PCM code definition Each device can only solve the voice format of the signed 8-bit or 12-bit raw PCM. And the MCU will take the voice code 80H as the end code. So each PCM code section must be ended with the end code 80H. D7 VM BL3 FR7 3/4 ST7 WBS RE7 A_R D6 FR BL2 FR6 3/4 ST6 D5 3/4 BL1 FR5 ST13 ST5 D4 3/4 BL0 FR4 ST12 ST4 D3 3/4 FR3 ST11 ST3 D2 3/4 FR2 ST10 ST2 D1 CH1 FR9 FR1 ST9 ST1 RE9 RE1 VR9 D0 CH0 FR8 FR0 ST8 ST0 RE8 RE0 VR8
A s a m p lin g d a ta c o d e ; B m e a n s o n e d a ta b y te . 1 2 - B it 1H 1M 1L 2L 2H 2M 3H 3M 3L
A s a m p lin g d a ta c o d e N o te : " 1 H " H ig h N ib b le " 1 M " M id d le N ib b le " 1 L " L o w N ib b le
Name 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH
Function Channel number selection (CHAN) Frequency number high byte (FreqNH) Frequency number low byte (FreqNL) Start address high byte (AddrH) Start address low byte (AddrL) Repeat number high byte (RepH) Repeat number low byte (RepL) Control register (ENV)
FR11 FR10
RE14 RE13 RE12 RE11 RE10 RE6 3/4 3/4 3/4 RE5 3/4 RE4 3/4 RE3 RE2
ENV1 ENV0
Right volume control (RVC)
VR7
VR6
VR5
VR4
VR3
VR2
VR1
VR0
Wavetable Register Memory Map (20h~2Ah)
ADPCM
Address Offset 30H 31H 32H 33H 34H Register Name ADR XSPL XSPH ADPC ADPS R/W W W W R/W R Default Value xxxx xxxx 0000 0000 0000 0000 00x0 xx00 0000 1111 Description ADPCM Data Register Xn + SP Initial Register Low Byte Xn + SP Initial Register High Byte ADPCM Decoder control register ADPCM Decoder Status Register
HT-ADPCM Decoder Registers
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b7 W B R 1 _ E m p ty W B R 0 _ E m p ty A D R 1 _ E m p ty b0 A D R 0 _ E m p ty
A D P S R e g is te r
V o ic e c h a n n e l 0 , A D P C M 0 : n o n e m p ty 1 : e m p ty D a ta E m p ty F la g D a ta E m p ty F la g
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V o ic e c h a n n e l 1 , A D P C M 0 : n o n e m p ty 1 : e m p ty V o ic e c h a n n e l 0 , W B R 0 : n o n e m p ty 1 : e m p ty Vo 0: 1: No
D a ta E m p ty F la g
ic e c h a n n e l 1 , W B R D a ta E m p ty F la g n o n e m p ty e m p ty t im p le m e n te d , r e a d a s " 0 "
ADPS (33H) - ADPCM Status Register
External RC Oscillation Converter
An external RC oscillation converter is implemented in certain devices and is a function which allows touch switch functions to be implemented. When used in conjunction with the Analog Switch function up to eight touch switches can be implemented. External RC Oscillation Converter Operation The RC oscillation converter is composed of two 16-bit count-up programmable timers. One is Timer A and the other is counter known as Timer B. The RC oscillation converter is enabled when the RCO bit, which is bit 1 of the RCOCR register, is set high. The RC oscillation converter will then be composed of four registers, TMRAL, TMRAH, TMRBL and TMRBH. The Timer A clock source comes from the fSYS or fSYS/4, the choice of which is determined by bits in the RCOCCR register. The RC oscillation converter Timer B clock source comes from an external RC oscillator. As the oscillation frequency is dependent upon external capacitance and resistance values, it can therefore be used to detect the increased capacitance of a touch switch pad. There are six registers related to the RC oscillation converter. These are, TMR2H, TMR2L, RCOCCR, TMR4H, TMR4L and RCOCR. The internal timer clock is the input clock source for TMRAH and TMRAL, while the exb7 RCOM2 RCOM1 RCOM0
RCOCON
ternal RC oscillator is the clock source input to TMRBH and TMRBL. The OVB bit, which is bit 0 of the RCOCR register, decides whether the timer interrupt is sourced from either the Timer A overflows or Timer B overflow. When a timer overflow occurs, the RCOCF bit is set and an external RC oscillation converter interrupt occurs. When the RC oscillation converter Timer A or Timer B overflows, the RCOCON bit is automatically reset to zero and stops counting. The resistor and capacitor form an oscillation circuit and input to TMRBH and TMRBL. The RCOM0, RCOM1 and RCOM2 bits of RCOCCR define the clock source of Timer A. When the RCOCON bit, which is bit 4 of the RCOCCR register, is set high, Timer A and Timer B will start counting until Timer A or Timer B overflows. Now the timer counter will generate an interrupt request flag which is bit RCOCF, bit 5 of the INTCH register. Both Timer A and Timer B will then stop counting and the RCOCON bit will automatically be reset to 0 at the same time. Note that if the RCOCON bit is high, the TMRAH, TMRAL, TMRBH and TMRBL registers cannot be read or written to.
b0 RCOCCR R e g is te r U n d e fin e d , r e a d a s z e r o R C O s c illa to r C o n v e r te r E n a b le 1 : E n a b le 0 : D is a b le T im e r A C lo c k S o u r c e S e le c t RCOM2 RCOM1 RCOM0 0 0 0 0 0 1 0 1 0 : : : 1 1 1
fS Y S (fO S C /2 ) fS Y S /4 (fO S C /8 ) U n d e fin e d : U n d e fin e d
RCOCCR Register
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b7 b0 ASON1ASON0 RCOCR R e g is te r
In te r r u p t S o u r c e S e le c t 1 : T im e r B o v e r flo w 0 : T im e r A o v e r flo w
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R C C o n v e rte r M o d e 1 : E n a b le 0 : D is a b le U n d e fin e d , r e a d a s z e r o
RCOCR Register
S1 S2 O VB=0 T im e r A TON T im e r B RC OSC O u tp u t E x te r n a l R C O s c illa tio n C o n v e r te r In te r r u p t
S y s te m S y s te m
C lo c k C lo c k /4
O VB=1 R esetR C O C O N
Programming Considerations As the 16-bit Timers have both low byte and high byte timer registers, accessing these registers is carried out in a specific way. It must be noted that when using instructions to preload data into the low byte registers, namely TMRAL or TMRAL, the data will only be placed into a low byte buffer and not directly into the low byte register. The actual transfer of the data into the low byte register is only carried out when a write to its associated high byte register, namely TMRAH or TMRBH, is executed. However, using instructions to preload data into the high byte timer register will result in the data being
directly written to the high byte register. At the same time the data in the low byte buffer will be transferred into its associated low byte register. For this reason, when preloading data into the 16-bit timer registers, the low byte should be written first. It must also be noted that to read the contents of the low byte register, a read to the high byte register must first be executed to latch the contents of the low byte buffer into its associated low byte register. After this has been done, the low byte register can be read in the normal way. Note that reading the low byte timer register will only result in reading the previously latched contents of the low byte buffer and not the actual contents of the low byte timer register.
Program Example External RC oscillation converter mode example program - Timer A overflow: clr RCOCCR mov a, 00000010b ; mov RCOCR,a clr intch.5 ; mov a, low (65536-1000) ; mov tmral, a ; mov a, high (65536-1000) mov tmrah, a mov a, 00h ; mov tmrbl, a mov a, 00h mov tmrbh, a mov a, 00110000b ; mov RCOCCR, a p10: clr wdt Snz intch.5 ; jmp p10 clr intch.5 ; ; Program continue
Enable External RC oscillation mode and set Timer A overflow Clear External RC Oscillation Converter interrupt request flag Give timer A initial value Timer A count 1000 time and then overflow
Give timer B initial value
Timer A clock source=fSYS/4 and timer on
Polling External RC Oscillation Converter interrupt request flag Clear External RC Oscillation Converter interrupt request flag
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Analog Switch
There are 8 analog switch lines in the microcontroller for K0~K7 for HT37Q70/60/50/40/30, except HT37Q20 which only have 4 analog switch lines for K0~K3 and the Analog Switch control register, which is mapped to the data memory. All of these Analog Switch lines can be used for touch key input keys.
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b7
b0 ASON3ASON2ASON1ASON0
ASCR
R e g is te r ASON0 0 1 0 1 0 1 0 1 X
A n a lo g S w itc h S e le c t ASON3 ASON2 ASON1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 0 1 X 1 X U n d e fin e d , r e a d a s z e r o
K0o K1o K2o K3o K4o K5o K6o K7o A ll o
n,o n,o n,o n,o n,o n,o n,o n,o ff, O
th e th e th e th e th e th e th e th e SC
rs o rs o rs o rs o rs o rs o rs o rs o o ff
ff ff ff ff ff ff ff ff
Analog Switch Control Register - ASCR
ASON
K0 K1 K2 K3 K4 K5 K6 K7 RCOUT
RR RC
T .G .1 T .G .2 T .G .3 T .G .4 T .G .5 T .G .6 T .G .7 T .G .8
CC
T im e r B
Analog Switch
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Configuration Options
Configuration options refer to certain options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT-MDS software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. All options must www..com be defined for proper system function, the details of which are shown in the table. No. 1 2 3 4 5 6 7 8 9 Watchdog Timer: enable or disable Watchdog Timer clock source: T1 (fOSC/8) or RC OSC CLRWDT instructions: 1 or 2 instructions PA0~PA7: wake-up enable or disable (bit option) PA, PB, PC and PD: pull-high enable or disable (port numbers are device dependent) System oscillator: Xtal Mode or RC Mode LVR function: enable or disable LVR function: 3.3V/2.2V Share PIN - PA5/INT : Enable (INT)/Disable (PA5) R to F Function : enable or normal I/O (PD) R to F_ Analog Switch: enable or normal I/O (PC) K0 Enable and PC1~7 K0~1 Enable and PC2~7 K0~2 Enable and PC3~7 K0~3 Enable and PC4~7 K0~4 Enable and PC5~7 K0~5 Enable and PC6~7 K0~6 Enable and PC7 K0~7 Enable Function
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Application Circuits
V V
DD DD
10W
47mF
47mF 0 .1 m F
E x te rn a l P o w e r A M P C ir c u it
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VDD OSC1 OSC2 V VDD VD D_DAC
0 .1 m F
50kW
0 .1 m F
RCH A u d _ in *R C H V b ia s 50kW
10mF
2 3
IN
8 OUTN VDD
1 7
OUTN SPK (8 W ) OUTP
H T82V733 VREF
OUTP
10mF 5
CE In te r n a l P o w e r A M P C ir c u it S peaker (8 W )
DD
4
VD D_AM P 47mF 0 .1 m F SP+ SPV 100kW RES 0 .1 m F
DD
VSS VSS VSS_D AC VSS_AM P
H T 3 7 Q 7 0 /6 0 /5 0 /4 0 /3 0 /2 0
Note: If user has used internal power amplifier circuit, need to add two capacitances (47mF, 0.1mF) that be connected between VCCA2 and VSS. HT37Q20 cant apply the internal power amplifier circuit application because it dont integrated power amplifier. User need use external power amplifier circuit with HT37Q20. * In application circuit, the RCH pin connect internal power amplifier circuit or external power amplifier circuit individually.
V
DD
10W 47mF VDD OSC1 V OSC2 SPK V
DD
0 .1 m F
VDD
VD D_DAC
1 1 .0 5 9 M H z
DD
(8 W ) VD D_AM P RCH 1kW 750W
V 100kW
DD
RES 0 .1 m F
VSS VSS VSS_D AC VSS_AM P
H T 3 7 Q 7 0 /6 0 /5 0 /4 0 /3 0 /2 0
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Instruction Set
Introduction C e n t ra l t o t he s uc c es s f ul oper a t i on o f a n y microcontroller is its instruction set, which is a set of program www..com instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 11.059MHz system oscillator, most instructions would be implemented within 0.723ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instructions would be CLR PCL or MOV PCL, A. For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the subroutine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
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Bit Operations The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port www..comcan be directly set high or low using either the SET pins [m].i or CLR [m].i instructions respectively. The feature removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used. Table Read Operations Data storage is normally implemented by using registers. However, when working with large amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the HALT instruction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address
Mnemonic Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] INCA [m] INC [m] DECA [m] DEC [m]
Description Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory
Cycles 1 1Note 1 1 1Note 1 1 1Note 1 1Note 1Note 1 1 1 1Note 1Note 1Note 1 1 1 1Note 1 1 1Note 1 1Note
Flag Affected Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z
Logic Operation
Increment & Decrement
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Mnemonic Rotate RRA [m] RR [m] RRCA [m] www..com [m] RRC RLA [m] RL [m] RLCA [m] RLC [m] Data Move MOV A,[m] MOV [m],A MOV A,x Bit Operation CLR [m].i SET [m].i Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Table Read TABRDC [m] TABRDL [m] Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode 1 1Note 1Note 1 1 1 1Note 1 1 None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory 2Note 2Note None None Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt 2 1Note 1note 1Note 1Note 1Note 1Note 1Note 1Note 2 2 2 2 None None None None None None None None None None None None None Clear bit of Data Memory Set bit of Data Memory 1Note 1Note None None Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC 1 1Note 1 None None None Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry 1 1Note 1 1Note 1 1Note 1 1Note None None C C None None C C Description Cycles Flag Affected
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the CLR WDT1 and CLR WDT2 instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both CLR WDT1 and CLR WDT2 instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.
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Instruction Definition
ADC A,[m] Description Add Data Memory to ACC with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ACC + [m] + C OV, Z, AC, C Add ACC to Data Memory with Carry The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. [m] ACC + [m] + C OV, Z, AC, C Add Data Memory to ACC The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. ACC ACC + [m] OV, Z, AC, C Add immediate data to ACC The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. ACC ACC + x OV, Z, AC, C Add ACC to Data Memory The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. [m] ACC + [m] OV, Z, AC, C Logical AND Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND [m] Z Logical AND immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. ACC ACC AND x Z Logical AND ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory. [m] ACC AND [m] Z
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Affected flag(s) ADCM A,[m] Description Operation Affected flag(s) ADD A,[m] Description Operation Affected flag(s) ADD A,x Description Operation Affected flag(s) ADDM A,[m] Description Operation Affected flag(s) AND A,[m] Description Operation Affected flag(s) AND A,x Description Operation Affected flag(s) ANDM A,[m] Description Operation Affected flag(s)
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CALL addr Description Subroutine call Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruction. Stack Program Counter + 1 Program Counter addr None Clear Data Memory Each bit of the specified Data Memory is cleared to 0. [m] 00H None Clear bit of Data Memory Bit i of the specified Data Memory is cleared to 0. [m].i 0 None Clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF Pre-clear Watchdog Timer The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no effect. WDT cleared TO 0 PDF 0 TO, PDF
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Operation Affected flag(s) CLR [m] Description Operation Affected flag(s) CLR [m].i Description Operation Affected flag(s) CLR WDT Description Operation
Affected flag(s) CLR WDT1 Description
Operation
Affected flag(s) CLR WDT2 Description
Operation
Affected flag(s)
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CPL [m] Description Operation Affected flag(s) www..com CPLA [m] Description Complement Data Memory Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] [m] Z Complement Data Memory with result in ACC Each bit of the specified Data Memory is logically complemented (1s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC [m] Z Decimal-Adjust ACC for addition with result in Data Memory Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. [m] ACC + 00H or [m] ACC + 06H or [m] ACC + 60H or [m] ACC + 66H C Decrement Data Memory Data in the specified Data Memory is decremented by 1. [m] [m] - 1 Z Decrement Data Memory with result in ACC Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] - 1 Z Enter power down mode This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. TO 0 PDF 1 TO, PDF
Operation Affected flag(s) DAA [m] Description
Operation
Affected flag(s) DEC [m] Description Operation Affected flag(s) DECA [m] Description Operation Affected flag(s) HALT Description
Operation Affected flag(s)
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INC [m] Description Operation Affected flag(s) Increment Data Memory Data in the specified Data Memory is incremented by 1. [m] [m] + 1 Z Increment Data Memory with result in ACC Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC [m] + 1 Z Jump unconditionally The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Program Counter addr None Move Data Memory to ACC The contents of the specified Data Memory are copied to the Accumulator. ACC [m] None Move immediate data to ACC The immediate data specified is loaded into the Accumulator. ACC x None Move ACC to Data Memory The contents of the Accumulator are copied to the specified Data Memory. [m] ACC None No operation No operation is performed. Execution continues with the next instruction. No operation None Logical OR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR [m] Z
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Description Operation Affected flag(s) JMP addr Description
Operation Affected flag(s) MOV A,[m] Description Operation Affected flag(s) MOV A,x Description Operation Affected flag(s) MOV [m],A Description Operation Affected flag(s) NOP Description Operation Affected flag(s) OR A,[m] Description Operation Affected flag(s)
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OR A,x Description Operation Affected flag(s) www..com ORM A,[m] Description Operation Affected flag(s) RET Description Operation Affected flag(s) RET A,x Description Operation Affected flag(s) RETI Description Logical OR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator. ACC ACC OR x Z Logical OR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory. [m] ACC OR [m] Z Return from subroutine The Program Counter is restored from the stack. Program execution continues at the restored address. Program Counter Stack None Return from subroutine and load immediate data to ACC The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Program Counter Stack ACC x None Return from interrupt The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed before returning to the main program. Program Counter Stack EMI 1 None Rotate Data Memory left The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 None Rotate Data Memory left with result in ACC The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 [m].7 None
Operation Affected flag(s) RL [m] Description Operation Affected flag(s) RLA [m] Description
Operation Affected flag(s)
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RLC [m] Description Operation Rotate Data Memory left through Carry The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. [m].(i+1) [m].i; (i = 0~6) [m].0 C C [m].7 C Rotate Data Memory left through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.(i+1) [m].i; (i = 0~6) ACC.0 C C [m].7 C Rotate Data Memory right The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 None Rotate Data Memory right with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 [m].0 None Rotate Data Memory right through Carry The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. [m].i [m].(i+1); (i = 0~6) [m].7 C C [m].0 C Rotate Data Memory right through Carry with result in ACC Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. ACC.i [m].(i+1); (i = 0~6) ACC.7 C C [m].0 C
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Affected flag(s) RLCA [m] Description
Operation
Affected flag(s) RR [m] Description Operation Affected flag(s) RRA [m] Description
Operation Affected flag(s) RRC [m] Description Operation
Affected flag(s) RRCA [m] Description
Operation
Affected flag(s)
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SBC A,[m] Description Subtract Data Memory from ACC with Carry The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] - C OV, Z, AC, C Subtract Data Memory from ACC with Carry and result in Data Memory The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] - C OV, Z, AC, C Skip if decrement Data Memory is 0 The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] - 1 Skip if [m] = 0 None Skip if decrement Data Memory is zero with result in ACC The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. ACC [m] - 1 Skip if ACC = 0 None Set Data Memory Each bit of the specified Data Memory is set to 1. [m] FFH None Set bit of Data Memory Bit i of the specified Data Memory is set to 1. [m].i 1 None
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Affected flag(s) SBCM A,[m] Description
Operation Affected flag(s) SDZ [m] Description
Operation Affected flag(s) SDZA [m] Description
Operation Affected flag(s) SET [m] Description Operation Affected flag(s) SET [m].i Description Operation Affected flag(s)
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SIZ [m] Description Skip if increment Data Memory is 0 The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. [m] [m] + 1 Skip if [m] = 0 None Skip if increment Data Memory is zero with result in ACC The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] + 1 Skip if ACC = 0 None Skip if bit i of Data Memory is not 0 If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Skip if [m].i 0 None Subtract Data Memory from ACC The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - [m] OV, Z, AC, C Subtract Data Memory from ACC with result in Data Memory The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. [m] ACC - [m] OV, Z, AC, C Subtract immediate data from ACC The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. ACC ACC - x OV, Z, AC, C
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Affected flag(s) SIZA [m] Description
Operation Affected flag(s) SNZ [m].i Description
Operation Affected flag(s) SUB A,[m] Description
Operation Affected flag(s) SUBM A,[m] Description
Operation Affected flag(s) SUB A,x Description
Operation Affected flag(s)
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SWAP [m] Description Operation Affected flag(s) Swap nibbles of Data Memory The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 [m].7 ~ [m].4 None Swap nibbles of Data Memory with result in ACC The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. ACC.3 ~ ACC.0 [m].7 ~ [m].4 ACC.7 ~ ACC.4 [m].3 ~ [m].0 None Skip if Data Memory is 0 If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Skip if [m] = 0 None Skip if Data Memory is 0 with data movement to ACC The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. ACC [m] Skip if [m] = 0 None Skip if bit i of Data Memory is 0 If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Skip if [m].i = 0 None Read table (current page) to TBLH and Data Memory The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None Read table (last page) to TBLH and Data Memory The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. [m] program code (low byte) TBLH program code (high byte) None
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Description Operation Affected flag(s) SZ [m] Description
Operation Affected flag(s) SZA [m] Description
Operation Affected flag(s) SZ [m].i Description
Operation Affected flag(s) TABRDC [m] Description Operation Affected flag(s) TABRDL [m] Description Operation Affected flag(s)
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XOR A,[m] Description Operation Affected flag(s) www..com XORM A,[m] Description Operation Affected flag(s) XOR A,x Description Operation Affected flag(s) Logical XOR Data Memory to ACC Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR [m] Z Logical XOR ACC to Data Memory Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory. [m] ACC XOR [m] Z Logical XOR immediate data to ACC Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. ACC ACC XOR x Z
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Package Information
20-pin SOP (300mil) Outline Dimensions
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A
20
11
B
1
C C'
10
G H
D E F
a
* MS-013
Symbol A B C C D E F G H a
Dimensions in mil Min. 393 256 12 496 3/4 3/4 4 16 8 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 512 104 3/4 12 50 13 8
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28-pin SOP (300mil) Outline Dimensions
28
15 B
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A
1
14
C C' G H D E F
a
* MS-013
Symbol A B C C D E F G H a
Dimensions in mil Min. 393 256 12 697 3/4 3/4 4 16 8 0 Nom. 3/4 3/4 3/4 3/4 3/4 50 3/4 3/4 3/4 3/4 Max. 419 300 20 713 104 3/4 12 50 13 8
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48-pin SSOP (300mil) Outline Dimensions
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A
48
25 B
1 C C'
24
G H a F
D E
Symbol A B C C D E F G H a
Dimensions in mil Min. 395 291 8 613 85 3/4 4 25 4 0 Nom. 3/4 3/4 3/4 3/4 3/4 25 3/4 3/4 3/4 3/4 Max. 420 299 12 637 99 3/4 10 35 12 8
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64-pin QFP (14mm20mm) Outline Dimensions
C
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D 51 33 G
H
I 52 32 F A B E
64
20 K a J 1 19
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 18.8 13.9 24.8 19.9 3/4 3/4 2.5 3/4 3/4 1.15 0.1 0 Nom. 3/4 3/4 3/4 3/4 1 0.4 3/4 3/4 0.1 3/4 3/4 3/4 Max. 19.2 14.1 25.2 20.1 3/4 3/4 3.1 3.4 3/4 1.45 0.2 7
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80-pin LQFP (10mm10mm) Outline Dimensions
C
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D 60
41
G
H
I 61 40
F A B
E
80
21 K 20 1 a J
Symbol A B C D E F G H I J K a
Dimensions in mm Min. 11.9 9.9 11.9 9.9 3/4 3/4 1.35 3/4 3/4 0.45 0.1 0 Nom. 3/4 3/4 3/4 3/4 0.4 0.16 3/4 3/4 0.1 3/4 3/4 3/4 Max. 12.1 10.1 12.1 10.1 3/4 3/4 1.45 1.6 3/4 0.75 0.2 7
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
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A
B
C
T1
SOP 20W, SOP 28W (300mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0+0.5/-0.2 2.00.5 24.8+0.3/-0.2 30.20.2
SSOP 48W Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.00.1 13.0+0.5/-0.2 2.00.5 32.2+0.3/-0.2 38.20.2
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Carrier Tape Dimensions
D
E
P0
P1
t
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F W
C
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SOP 20W Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Description Carrier Tape Width Dimensions in mm 24.0+0.3/-0.1 12.00.1 1.750.10 11.50.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.00.1 2.00.1 10.80.1 13.30.1 3.20.1 0.300.05 21.30.1
SOP 28W (300mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5+0.1/-0.0 1.50+0.25/-0.00 4.00.1 2.00.1 10.850.10 18.340.10 2.970.10 0.350.01 21.30.1
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D
E F W C B0
P0
P1
t
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D1
P K2 A0
K1
R e e l H o le ( C ir c le ) p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e . R e e l H o le ( E llip s e ) IC
SSOP 48W Symbol W P E F D D1 P0 P1 A0 B0 K1 K2 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 32.00.3 16.00.1 1.750.10 14.20.1 2 Min. 1.50+0.25/-0.00 4.00.1 2.00.1 12.00.1 16.20.1 2.40.1 3.20.1 0.350.05 25.50.1
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Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) G Room, 3 Floor, No.1 Building, No.2016 Yi-Shan Road, Minhang District, Shanghai, China 201103 Tel: 86-21-5422-4590 Fax: 86-21-5422-4705 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, Gaoxin M 2nd, Middle Zone Of High-Tech Industrial Park, ShenZhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538, USA Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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